Originally Posted by Clocknut
why cant they reduce the bit width to 512bit and able to do it on GPU PCB without expensive interposer?
the 1024bit bus is divided into 128bit channels internally, so technically its an 8channel bus.
they probably want to maintain the channel width to decrease the access latency by interleaving them, the channel access aren't necessarily synchronous thus allowing multiple transactions individually.
so if they wanted to shrink the bus to 512bit, they'd either need to re-build the design to allow 64bit internal channels, or increase access latency by reducing the total number of channels.
edit: plus they're probably aiming for an even denser chip, pin density would increase as they shrink the package to smaller sizes.
integrating HBMs to compact devices like phones would become their targets sooner or later, which will mean they'll need to get it even smaller.
trolling an adult is very dangerous, don't try it at home nor at work. you don't want to play tag with a rabid man.
Last edited by epic1337; 03-20-2019 at 06:53 AM.