[TPU] PCI-SIG Announces PCIe 6.0 Specification - Page 2 - Overclock.net - An Overclocking Community

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[TPU] PCI-SIG Announces PCIe 6.0 Specification

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post #11 of 33 (permalink) Old 06-19-2019, 01:42 AM
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More in depth explanation about technologies behind the PCIe 6.0:

https://www.anandtech.com/show/14559...o-land-in-2021
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post #12 of 33 (permalink) Old 06-19-2019, 02:31 AM
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Wow, I'm not too knowledgeable on the matters at hand, but with how they were talking about 4 and 5 (particularly seeing some people saying even 5 would probably ditch copper a few years ago), I'm surprised 6 is still on copper.

I wonder if bandwidth can grow fast enough that (some) consumer level graphics cards and motherboards can be reduced to having 8x slot sizes instead of 16x in the future? I'm sure board makers would love to have a bit of extra room to work with.


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post #13 of 33 (permalink) Old 06-19-2019, 03:03 AM
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Quote: Originally Posted by kyrie74 View Post
Don't forget the Radeon 5700 and the XT will also have PCIe 4.0.
That is more for marketing than actual need though.
Next iteration might matter. But at their performance level, I don't think so.

Quote: Originally Posted by Millillion View Post
Wow, I'm not too knowledgeable on the matters at hand, but with how they were talking about 4 and 5 (particularly seeing some people saying even 5 would probably ditch copper a few years ago), I'm surprised 6 is still on copper.

I wonder if bandwidth can grow fast enough that (some) consumer level graphics cards and motherboards can be reduced to having 8x slot sizes instead of 16x in the future? I'm sure board makers would love to have a bit of extra room to work with.
Today mid and low range already don't need x16 of PCIE 3.0. And it will take a couple of years for them to reach the high end performance for x16 lanes to matter.

PCIE 4.0 and above right now only matter to super high end/enterprise hardware, like titan rtx and above, quadro/radeon pro cards and high performance storage that actually need the high bandwidth to catch up with the hardware speed.
For the consumer, even x16 for the most part is an overkill.



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post #14 of 33 (permalink) Old 06-19-2019, 06:51 AM
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Quote: Originally Posted by EniGma1987 View Post
And with how much PCIE4 costs to implement, how much will this end up costing? They really should just break backwards compatibility at some point and move to optical connections to the slot and expansion cards for the sake of cost and ease of implementation.
Optical interfaces will make the situation worse instead of better. As a technology it has many good traits, but cost and ease of engineering aren't going to be among them for this use case.

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post #15 of 33 (permalink) Old 06-19-2019, 07:07 AM
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Quote: Originally Posted by Particle View Post
Optical interfaces will make the situation worse instead of better. As a technology it has many good traits, but cost and ease of engineering aren't going to be among them for this use case.
You dont need as many "pins" with optical though since you can send multiple modulated wavelengths through the same fiber. You also wouldnt need positive and negative pairs for noise rejection. You dont even have to run lines through the MB at all. For ATX form factor chassis compatibility, just have blank slots on the board for mounting location of the card with a optical connector near the CPU that you plug a cable into between there and the add on card. This could lead to future chassis form factors where GPUs wouldnt even need to mount the same and you dont even need the slot area on the MB since it just plugs in with a optical cable. No traces through the board and not needing nearly as many pinouts would save a ton of money on board design as well as space. The only thing this wouldnt work for is m.2 SSDs, but Im sure a solution could be thought of for connecting into them as well. Especially if we move to a different form factor and you dont have GPUs covering up MB space where SSDs would mount.


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post #16 of 33 (permalink) Old 06-19-2019, 07:09 AM
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we arent even close to maxing out 3.0 why do we need 6?

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post #17 of 33 (permalink) Old 06-19-2019, 07:11 AM
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Quote: Originally Posted by philhalo66 View Post
we arent even close to maxing out 3.0 why do we need 6?



3 has been maxed for quite a long time. GPUs are really the only thing lagging behind in this area. Shoot, even 4 is maxed out with NICs and sustained rate on SSDs and it isnt even available yet...

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post #18 of 33 (permalink) Old 06-19-2019, 07:26 AM
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Quote: Originally Posted by philhalo66 View Post
we arent even close to maxing out 3.0 why do we need 6?
So... a 400gbps network card needs a 6.0 x4 (5.0 x8, 4.0 x16).

Being able to take our existing 5GB/s PCI-e 4.0 x4 NVMe SSDs and putting them on 6.0 x1s would allow of much larger storage arrays with less hardware.

Infiniband is already looking at faster than terabit speeds.

AI/Learning GPUs and CPUs need interconnects this fast, which is why NVLink and Infinity Fabric exist in this setting.

Super computers as a whole, combining all of the above.

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post #19 of 33 (permalink) Old 06-19-2019, 08:41 AM
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i think folks are overlooking the basics here. PCI-E is a full-duplex serial bus. looking at just gpus, ssds, NIC, PCH and/or whatever I/Os a motherboard supports, is overlooking that it's primary function as bus is to interconnect all of them.

so keep jacking it up until the RAM becomes the bottleneck.

Remember the golden rule of statistics: A personal sample size of one is a sufficient basis upon which to draw universal conclusions.
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post #20 of 33 (permalink) Old 06-19-2019, 01:58 PM
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Quote: Originally Posted by kyrie74 View Post
Don't forget the Radeon 5700 and the XT will also have PCIe 4.0.
This is the kind of thing I'm most interested in. Why is the Radeon 5700 XT sporting GDDR6 memory instead of HBM? I hope this is the 2080Ti slayer.
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