[Tom's Hardware] Intel Reveals Three new Cutting-Edge Packaging Technologies - Overclock.net - An Overclocking Community

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[Tom's Hardware] Intel Reveals Three new Cutting-Edge Packaging Technologies

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post #1 of 11 (permalink) Old 07-10-2019, 10:20 PM - Thread Starter
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[Tom's Hardware] Intel Reveals Three new Cutting-Edge Packaging Technologies

Source: https://www.tomshardware.com/news/in...dio,39840.html

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Intel revealed three new packaging technologies at SEMICON West: Co-EMIB, Omni-Directional Interconnect (ODI) and Multi-Die I/O (MDIO). These new technologies enable massive designs by stitching together multiple dies into one processor. Building upon Intel's 2.5D EMIB and 3D Foveros tech, the technologies aim to bring near-monolithic power and performance to heterogeneous packages. For the data-center, that could enable a platform scope that far exceeds the die-size limits of single dies. 

The focus of semiconductors is usually on the process node itself, but packaging is one of the oft-unsung enablers of modern semiconductors. Ultimately a silicon chip is just part of a bigger system that requires power and data interconnection. Packaging, in that view, provides the physical interface between the processor and the motherboard – the board acts as a landing zone for the chip’s electrical signals and power supply. Intel stated a few years ago that its assembly and test R&D is bigger than the top two OSATs (outsourced assembly and test) combined.
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post #2 of 11 (permalink) Old 07-10-2019, 10:33 PM
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So, at least 2 years, before they can bring in any new architecture, which can run on this.

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post #3 of 11 (permalink) Old 07-10-2019, 10:43 PM - Thread Starter
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Quote: Originally Posted by ku4eto View Post
So, at least 2 years, before they can bring in any new architecture, which can run on this.
5 Foveros Lakefield chips should be out later this year or Q1 2020.

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post #4 of 11 (permalink) Old 07-10-2019, 11:33 PM
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So glue then?
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post #5 of 11 (permalink) Old 07-10-2019, 11:45 PM
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Pretty fancy way of saying "glue" there Intel...wonder how they intend to cool these Foveros chips, without them thermal throttling to hell?
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post #6 of 11 (permalink) Old 07-11-2019, 05:37 AM
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Quote: Originally Posted by GHADthc View Post
Pretty fancy way of saying "glue" there Intel...wonder how they intend to cool these Foveros chips, without them thermal throttling to hell?
Just pack a cheap Asetek AIO in the "boxed" version and ask a $200 premium lol. Honestly, even the current i7/i9/HEDT chips are barely coolable with regular air cooling so probably by setting a really low per-core baseclock and only boosting to any useful clocks when temps are low enough just like mobile SKU's

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post #7 of 11 (permalink) Old 07-11-2019, 06:11 AM
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the advantage in cooling of EMIB multi-chips is that it has a much larger surface area than a monolithic chip.

i'd like to see them get rid of the IGP from the processor die and do an EMIB out of it.
this way they can free up some package power from the CPU die and increase the IGP's size without affecting CPU yields.

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post #8 of 11 (permalink) Old 07-11-2019, 07:00 AM
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Quote: Originally Posted by epic1337 View Post
the advantage in cooling of EMIB multi-chips is that it has a much larger surface area than a monolithic chip.

i'd like to see them get rid of the IGP from the processor die and do an EMIB out of it.
this way they can free up some package power from the CPU die and increase the IGP's size without affecting CPU yields.
I think a big, attached, unused igpu helps with cooling the cores. So would a big cache.
This packaging could make for some beastly dgpus.

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post #9 of 11 (permalink) Old 07-11-2019, 07:20 AM
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Quote: Originally Posted by rluker5 View Post
I think a big, attached, unused igpu helps with cooling the cores. So would a big cache.
This packaging could make for some beastly dgpus.
true, but its very minor since silicon isn't really that good of a thermal conductor.
it would be better if cores were spaced a bit more, like adding more cache inbetween.

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post #10 of 11 (permalink) Old 07-11-2019, 08:03 AM
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Quote: Originally Posted by ku4eto View Post
So, at least 2 years, before they can bring in any new architecture, which can run on this.
And 3 years before someone finds an exploit because intel was too lazy to address exploits they knew about.

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