PCIe Generation 4 is just beginning to hit the market in processors and GPUs, yet many companies are already anticipating PCIe Gen 5 within a couple of years and the specification for PCIe Gen 6 is in development.
Amazingly enough, the PCI Special Interest Group (SIG) has set its goal to double data throughput in each of these generations, even as the industry pushes the limits of board and packaging technology. This is not an easy goal to achieve, but there's enough commitment and optimism by the PCI SIG members to maintain this pace.
The SIG announced PCIe 4.0 official compliance testing will be available this August. The PCIe Gen 4 spec supports 16 giga-transfers per second (GT/s) and the forthcoming Gen 5 doubles that to 32GT/s (using NRZ encoding). With PCIe Gen 6, the group plans to double the rate again to 64 GT/s per lane. To get to that speed, the committee chose to adopt the proven PAM4 signaling from the telecommunications industry for 56Gbits/s interfaces.
In particular, the timing of the new PCIe generations has a direct impact on two competing accelerator connection standards that allow CPUs and accelerators to share memory—the Cache Coherent Interface for Accelerators (CCIX
) and the Compute Express Link (CXL
The CCIX standard is available today and runs on PCIe Gen 4. Presently, the major silicon proponent for CCIX is Xilinx, but many other vendors have signed up for the CCIX group. Earlier this year
, Intel released the competing CXL specification that will run over PCIe Gen 5.