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[AnandTech] Intel Begins Commercial Shipments of 10nm Ice Lake CPUs to OEMs

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post #41 of 45 (permalink) Old 08-07-2019, 11:36 AM
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post #42 of 45 (permalink) Old 08-08-2019, 06:52 AM
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Quote: Originally Posted by rluker5 View Post
Here's an example of that trick I told Hwgeek: I ran my living room itx at 4.2ghz with xtu internal benchmark then cpuz benchmark, but it wasn't long enough so I stressed it for a while to get stable values. I then reduced the core clock to 3.3ghz and adjusted the volts to be the same and ran the xtu bench, then cpuz stress test. The xtu bench is all jumpy so I'll use the cpuz stress test numbers as an example.

Core tdp during 4.2Ghz stress was 85w, during 3.3Ghz was 68w. (85/68)*3.3=4.125 so apparently the chip is more efficient at 4.2ghz at the same volts, but not by much. The power scaling with instructions per second is near linear with the same cpu, software.

How does a higher ipc, with all else equal, resulting in higher ips consume power differently than higher clocks, with all else equal, resulting in higher ips? I've seen with my various atom mini pcs(z8300,z8500,n4100) that their performance scales close to linear with power. This 5775c test seems to agree. Maybe I'm missing something. It's easy to replicate with all sorts of software and hardware though. Makes the problem of making cpus go faster a little tougher if every instruction carries heat with it.

Intel has been getting more efficient over the years and AMD really has with Zen. And once they get the bugs ironed out 10nm should be able to efficiency away the extra heat from extra ips.
@WannaBeOCer is correct, more IPC does not inherently mean more power consumption. At the end of the day it is more likely to reduce consumption over time instead, or at least keep Perf/Watt the same.

If a Job takes 20 cycles and 10 of those are waiting for data, 5 are for operation one, and five are for operation two, then there are a few ways that you can optimize IPC.

If you reduce the waiting time for Data from 10 cycles to 8, then you can reduce Time on Task by 10%, from 20 to 18 cycles. This may bump the power usage slightly in long-term loads similar to HyperThreading (but the job gets done faster), but for short term loads it adheres to the typical race-to-sleep. During that 8 or 10 cycles wait it can not clock down much, but as soon as the whole job is done, it can, and it finishes sooner. this enables the CPU to clock down for longer periods of time by finishing it's work faster.

If you reduce the time it takes to complete operations one and two from 5 cycles to 4 cycles, then you actually get more performance for free. Fewer cycles used means fewer transistors flipped provided the same number of transistors are used, and that translates to both more performance and/or less power consumption, again depending on if it is a burst or long term load.

Inversely, if you find a way to get the same job done in fewer cycles with fewer transistors, you can do the same job both faster and for less power, which leads into;

If you create a new extension, such as AVX-256, then perhaps your two 5-cycle (128-bit) operations can be done in one 5-cycle operation. This will not affect all workloads, but it is targeted to specific jobs. It uses more transistors, but only when required to do so, and not always double the transistors for double the work. Doing this in our hypothetical 20 cycle example can reduce the workload to just 15 cycles. Once again, in the race to sleep, this is prefered, but in long term tasks, the total power over time will work out the same but the job finishes sooner; more performance for free.

All of these have the possibility to increase power consumption under load, but generally do so for an equal trade in time reduction. In our imperfect world however, we very rarely load an entire CPU to 100%, which is why we have SMT/HT. People who run their CPUs to the max typically only care about getting the job done, and more IPC does that. Those who use their CPUs in bursts, like Mobile, care about the race to sleep to get total consumption over time down. Remember that while increasing clocks to do the job is linear in it's power consumption, you need to increase voltage too, and that makes it logarithmic.

Final example for power over time and race to sleep;

CPU draws 100w under load.
CPU draws 5w idle.
CPU takes 1 hour to complete the job each day.
CPU draws 100wh + (23)5wh each day = 215wh/day.

Increase IPC by 50% with linear increase in consumption for equal work;

CPU draws 150w under load.
CPU draws 5w idle.
CPU takes 40m to complete the job each day.
CPU draws (.67)150wh + (23.3)5wh each day = 216.7wh/day

+1.7wh/day to get the job done in 2/3rds the time? Seems a good deal for me, and fantastic for anything that runs on a battery. They can chose to run a mix of efficiency improving IPC and performance improving IPC to get the desired result.

This is why AMD, Intel, and even Qualcomm are willing to give such higher boost clocks, if temporarily, on parts with such low base clocks. The idle power is so much less than the load power that it makes more sense to get the job done in a fraction the time, even at several times the cost during that time, than to stay in the "medium" power state for any length of time.

And these numbers are not that far from reality. Remember that while we may give the 9900k flack for being as hot as it is, it still only draws 8w idle;


And some quick-search reading material on short load power consumption efficiencies;
https://www.anandtech.com/show/11964...-updated-zen/4

And of course, finally, if you can increase IPC enough, then you can reduce clocks to hit a performance target, which means you can reduce voltage, which means Perf/Watt goes up massively.





TL;DR, making CPUs is hard, and this is only a fraction of what really defines perf/watt and perf/time. Looking at only IPC in a static vacuum is a very limited viewpoint that doesn't apply to reality. Node updates, node shrinks, process improvements, materials improvements, external efficiency improvements such as ram or storage... it all plays a part.

Quote: Originally Posted by rluker5 View Post
My comparison has same node, same volts, same hardware, same software, same external environment. Yours spans over modified process nodes and different volts. With all else equal, except for instructions per second, my comparison still stands and you can verify it yourself on any cpu (that you have) you choose. More instructions per second means more power consumed. More ipc is more instructions per second just like higher clocks or higher load.

Edit: After another quick test it appears that some methods of increasing ipc may be more efficient. I did a similar test ht on vs off to just increase ipc with a particular method and got a 26% performance improvement for 15% more power. Which is better than the closer to near 0 performance/power improvement I see comparing a z8500 atom to a n4100 atom I have. They would still need a more efficient node if you were to increase the heat output of a 9900ks by 10% though.
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post #43 of 45 (permalink) Old 08-08-2019, 12:22 PM
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Performing more instructions per second, over a period of time, does result in more power being consumed over that time. If all else is equal. It doesn't matter if you increase clocks, ipc or number of active cores. You can decrease power consumed by making the processor more efficient, but this doesn't invalidate the previous statement. This is not to say there aren't ways to have an equal amount of work more efficiently with a more advanced processor, but who upgrades their chip and doesn't increase their demand on it? Why upgrade it at all then?

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post #44 of 45 (permalink) Old 08-08-2019, 01:48 PM
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Quote: Originally Posted by rluker5 View Post
Performing more instructions per second, over a period of time, does result in more power being consumed over that time. If all else is equal. It doesn't matter if you increase clocks, ipc or number of active cores. You can decrease power consumed by making the processor more efficient, but this doesn't invalidate the previous statement. This is not to say there aren't ways to have an equal amount of work more efficiently with a more advanced processor, but who upgrades their chip and doesn't increase their demand on it? Why upgrade it at all then?
All else can never be equal. Transistors are not magic. They do, actually, perform a fixed function. They are purpose built devices, made from tools and resources. An ALU is a cluster of transistors layed out in such a way as to perform a series of math functions. An ALU can never hit peak IPC unless all supporting logic can feed it, and even then peak IPC may not be the best performing option; see Ice Lake.

It is possible to reduce the number of cycles something takes to complete, while also reducing the number of transistors required to do the job significantly. The shorter time to complete means that more performance is achieved. The fewer transistors mean less power is used in the same time period to complete that job. This remains true even if every single other thing is equal. To imply that doing more work always requires more power is to imply the inverse as well; that doing less takes less. That we have discovered the most efficient way to do everything. Bulldozer and Netburst would like to disagree on that, and are stunning examples of it.

The reason HT/SMT gives you a net-positive perf/watt is because CPUs are not as simple as you might think. If a Core has four ALUs and your program uses one, the CPU is still using Cache, the decoder, and all supporting parts, and none of those can clock down. HT/SMT gives those supporting parts that are already at full speed more work to do so that you may use more of your Core, but that increased work is cheaper than another core because of the inherent inefficiencies of code and CPU design. An FPGA for example would never have this problem.

-------------

We upgrade for many reasons.

If you were to look at a new CPU now, there are many things to consider. Total heat output/difficulty to cool, compatibility, power consumption, raw performance both multi and single, battery life, upgradability, and so on. Obviously you will chose the one best for your needs for the money you will spend.

But unless you are going to buy a CPU for BONIC or Folding, you probably are not going to run them 24/7. Even if you do compile, render, or game, I'm going to bet you do not do so on average more than maybe 5-8 hours a day. CPUs are nearly never under constant load even in those situations, and that is why I brought up Race to Sleep. Literally no one runs Prime95 24/7 for the life of their chip.

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post #45 of 45 (permalink) Old 08-08-2019, 08:41 PM
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Quote: Originally Posted by KyadCK View Post
All else can never be equal. Transistors are not magic. They do, actually, perform a fixed function. They are purpose built devices, made from tools and resources. An ALU is a cluster of transistors layed out in such a way as to perform a series of math functions. An ALU can never hit peak IPC unless all supporting logic can feed it, and even then peak IPC may not be the best performing option; see Ice Lake.

It is possible to reduce the number of cycles something takes to complete, while also reducing the number of transistors required to do the job significantly. The shorter time to complete means that more performance is achieved. The fewer transistors mean less power is used in the same time period to complete that job. This remains true even if every single other thing is equal. To imply that doing more work always requires more power is to imply the inverse as well; that doing less takes less. That we have discovered the most efficient way to do everything. Bulldozer and Netburst would like to disagree on that, and are stunning examples of it.

The reason HT/SMT gives you a net-positive perf/watt is because CPUs are not as simple as you might think. If a Core has four ALUs and your program uses one, the CPU is still using Cache, the decoder, and all supporting parts, and none of those can clock down. HT/SMT gives those supporting parts that are already at full speed more work to do so that you may use more of your Core, but that increased work is cheaper than another core because of the inherent inefficiencies of code and CPU design. An FPGA for example would never have this problem.

-------------

We upgrade for many reasons.

If you were to look at a new CPU now, there are many things to consider. Total heat output/difficulty to cool, compatibility, power consumption, raw performance both multi and single, battery life, upgradability, and so on. Obviously you will chose the one best for your needs for the money you will spend.

But unless you are going to buy a CPU for BONIC or Folding, you probably are not going to run them 24/7. Even if you do compile, render, or game, I'm going to bet you do not do so on average more than maybe 5-8 hours a day. CPUs are nearly never under constant load even in those situations, and that is why I brought up Race to Sleep. Literally no one runs Prime95 24/7 for the life of their chip.
That's all good and complicated. And I agree with most of it, but it is avoiding my point that an average buyer couldn't reasonably cool a hypothetical 5ghz 10900kf on 14+++ with Sunny Cove arch.
That statement assumes a lot will be , if not equal, quite similar. 14+++ would probably be another iteration with similar improvements as the previous + were.
Sunny Cove already looks power hungry for it's clocks and I think the main culprit is the extra electron powered 1s and 0s that it pushes per clock. The + likely wouldn't offset a .2Ghz (4%) increase in electrons/time much less 3 to 4 times that.

The heat of the 9900k already is a real problem. I checked out the 9900k overclock results and questions forum and saw a bunch of competent enthusiasts with delidded soldered chips and most with custom cooling loops. And bench temps in the 80s. Sure they may be having fun doing that, but it is too much for a lot of people. Those aren't average cooling setups. Excellent or awesome are more appropriate descriptions, not average like the Cooler Master 120mm AIO or Scythe Mugen I'm using.

Put a significantly hotter chip in the hands of some kid who just wants a high end gaming rig and expects the chip to perform as advertised with a big air cooler with lots of windows and rgb in the case and you have a reason for rma. You could also claim you were such a kid to try your luck to get better silicon. If Intel said "Just load it occasionally, or frequently with light loads. It's right there in the eula." there would be lawsuits.

And I doubt games will not be getting harder on cpus when the Ryzen consoles release.

But a refined 10nm or 7nm euv should help with this heat a bunch.

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