technically its not impossible to make the HBM into a shared LL cache to allow expandable DDR4 slots.
to begin with, most of Intel's Iris PRO uses this approach.
plus it would be advantageous to AMD too, the HBM IMC would be on the main chiplets, and the DDR4 IMC would be on the I/O die.
this way theres no latency penalty for the cached data, while the I/O IMC latency would be masked by the HBM.
trolling an adult is very dangerous, don't try it at home nor at work. you don't want to play tag with a rabid man.