[Anandtech] SK Hynix Announces 3.6 Gbps HBM2E Memory - Overclock.net - An Overclocking Community

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[Anandtech] SK Hynix Announces 3.6 Gbps HBM2E Memory

 
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post #1 of 10 (permalink) Old 08-12-2019, 12:11 PM - Thread Starter
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[Anandtech] SK Hynix Announces 3.6 Gbps HBM2E Memory

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SK Hynix this morning has thrown their hat into the ring as the second company to announce memory based on the HBM2E standard. While the company isn’t using any kind of flash name for the memory (ala Samsung’s Flashbolt), the idea is the same: releasing faster and higher density HBM2 memory for the next generation of high-end processors. Hynix’s HBM2E memory will reach up to 3.6 Gbps, which as things currently stand, will make it the fastest HBM2E memory on the market when it ships in 2020.
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Hoping this brings down costs of HMB2 memory as more competition and supply enter the chain. Also hoping we see more HBM2 on package for APU and such.
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post #2 of 10 (permalink) Old 08-13-2019, 02:21 AM
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While HBM2 can be interesting in APUs, it might limit upgradability.
Considering a laptop with an APU. You will need to manufacture 3 different version of the exact same CPU with different memory, because the laptop manufacturer can't just add more memory once they get the chip to offer their customers several memory options.
It could drive costs up for APUs or laptops because of the choices of memory are limited by the APU.


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post #3 of 10 (permalink) Old 08-13-2019, 03:06 AM
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Quote: Originally Posted by Defoler View Post
While HBM2 can be interesting in APUs, it might limit upgradability.
Considering a laptop with an APU. You will need to manufacture 3 different version of the exact same CPU with different memory, because the laptop manufacturer can't just add more memory once they get the chip to offer their customers several memory options.
That shouldn't be much difficult considering there are 7(?) different versions of Skylake i7 mobile performance processors that differ based on the graphic processors alone.

And with AMD's chiplet design, they should be able to design as many lego blocks as they may wish to.

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It could drive costs up for APUs or laptops because of the choices of memory are limited by the APU.
That has already been matched against the profitability from selling multiple chips with varying flavors and it seems the latter won. Creating processor with varying HBM memory shouldn't be at all difficult.

#2 their debt is insane, even for a "diverse field" company. They cannot even afford to service the debt maintenance let alone make an actual dent in the debt itself. - Internet Stranger
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post #4 of 10 (permalink) Old 08-13-2019, 03:42 AM
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technically its not impossible to make the HBM into a shared LL cache to allow expandable DDR4 slots.
to begin with, most of Intel's Iris PRO uses this approach.

plus it would be advantageous to AMD too, the HBM IMC would be on the main chiplets, and the DDR4 IMC would be on the I/O die.
this way theres no latency penalty for the cached data, while the I/O IMC latency would be masked by the HBM.

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post #5 of 10 (permalink) Old 08-13-2019, 05:59 AM
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Quote: Originally Posted by Namwons View Post
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Hoping this brings down costs of HMB2 memory as more competition and supply enter the chain. Also hoping we see more HBM2 on package for APU and such.
HBM has an extra logic chip and interposer that is extra vs typical DRAM so I wouldn't expect it to be on par dollar wise.


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post #6 of 10 (permalink) Old 08-13-2019, 08:24 AM
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Quote: Originally Posted by epic1337 View Post
technically its not impossible to make the HBM into a shared LL cache to allow expandable DDR4 slots.
to begin with, most of Intel's Iris PRO uses this approach.

plus it would be advantageous to AMD too, the HBM IMC would be on the main chiplets, and the DDR4 IMC would be on the I/O die.
this way theres no latency penalty for the cached data, while the I/O IMC latency would be masked by the HBM.

If AMD were to use a normal memory controller and dimms as well as an HBM memory cache I would expect all data to still flow through the IO die so that it could manage what is in the HBM and what is being pulled from DDR4 and maintain the coherency between all the caches throughout the dies and package.

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post #7 of 10 (permalink) Old 08-13-2019, 08:30 AM
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Quote: Originally Posted by huzzug View Post
That shouldn't be much difficult considering there are 7(?) different versions of Skylake i7 mobile performance processors that differ based on the graphic processors alone.
You have 7 different skylake i7 mobile chips, which come with different tdp, core count, speed and gpu. Now add 3 version for each chip, one with 8GB of HBM2E, one with 16GB, one with 32GB. That gives you now 21 chips.
This will escalate prices.
Allowing to connect extra DDR4 memory, will directly make the memory much slower, which will completely negate the whole reason to use HBM2E.


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post #8 of 10 (permalink) Old 08-13-2019, 09:47 AM
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Quote: Originally Posted by EniGma1987 View Post
If AMD were to use a normal memory controller and dimms as well as an HBM memory cache I would expect all data to still flow through the IO die so that it could manage what is in the HBM and what is being pulled from DDR4 and maintain the coherency between all the caches throughout the dies and package.
yes and no, it would depend on how it is implemented.
if it functioned like a normal cache (e.g. the HBM is invisible to users) then it would only evict data from the cache when its full, and only access DRAM when it misses.
if it functioned like a DRAM extension (e.g. HBM+DRAM are additive), it will occasionally access the DRAM to synchronize but it could be minimized, so you'd still get the benefit of high-speed on-package cache.

edit: Intel's eDRAM is configured like the first one, and you can see how much Broadwell-C benefited from a meager 128MB cache.

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Last edited by epic1337; 08-13-2019 at 09:55 AM.
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post #9 of 10 (permalink) Old 08-13-2019, 10:46 AM
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Quote: Originally Posted by Defoler View Post
You have 7 different skylake i7 mobile chips, which come with different tdp, core count, speed and gpu. Now add 3 version for each chip, one with 8GB of HBM2E, one with 16GB, one with 32GB. That gives you now 21 chips.
This will escalate prices.
Allowing to connect extra DDR4 memory, will directly make the memory much slower, which will completely negate the whole reason to use HBM2E.
The Skylake performance bracket for mobile already has 7 chips that are quad cores. The difference in TDP comes from clock speed and the graphic chips. They could only launch 8GB variants for dual / quad core and still have the same variations.

As for the performance impact of additional memory controller, that already affects the current chips without the HBM.

#2 their debt is insane, even for a "diverse field" company. They cannot even afford to service the debt maintenance let alone make an actual dent in the debt itself. - Internet Stranger
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post #10 of 10 (permalink) Old 08-17-2019, 09:47 PM
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The successor of GV100 from nvidia will probably adopt 2 of these stack to give them massive 920GB/s and 32GB of capacity.


This will be a huge step for them as having less stack means reduced yield loss for the HBM / GPU.

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