[The Register] AMD agrees to cough up $35-a-chip payout over eight-core Bulldozer advertising fiasco - Page 2 - Overclock.net - An Overclocking Community

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[The Register] AMD agrees to cough up $35-a-chip payout over eight-core Bulldozer advertising fiasco

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post #11 of 166 (permalink) Old 08-27-2019, 03:39 PM
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A court of law shouldn't decide such a technical issue.

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post #12 of 166 (permalink) Old 08-27-2019, 03:43 PM
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Quote: Originally Posted by WannaBeOCer View Post
47% agree with me on the definition of a core.
Any pols a goal...
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post #13 of 166 (permalink) Old 08-27-2019, 04:05 PM
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For example, if it was an actual criminal case they would have to prove beyond reasonable doubt that AMD didn't design two-cores.

A core would have seperate control units(thread/context manager), separate instruction buses, separate data buses, and separate execution datapaths.

Design of the Two-Core x86-64 AMD “Bulldozer” Module in 32 nm SOI CMOS;
"Each core is dedicated to a thread and contains a four-wide integer execution unit, issue/retire logic, 16KB four-way set associative L1 data cache, and a load/store unit."

Each core contains issue/retire logic => separate instruction buses. // Not something a single core would do, so not a single core.
Each core is dedicated to one of two threads => separate control units. // Not something a single core would do, so not a single core.
Each core has a data bus implied by the unshared L1d/LSU => separate data buses. // Not something a single core would do, so not a single core.
Each core has a four-wide integer datapath => seperate execution datapaths. // Not something a single core would do, so not a single core.

I have beyond reasonable doubt proven via published IEEE documents that AMD is innocent of false advertising. On any of the Zambezi, Vishera, Centurion SKUs selected for this lawsuit.


Last edited by Seronx; 08-27-2019 at 04:10 PM.
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post #14 of 166 (permalink) Old 08-27-2019, 04:08 PM
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In AMD’s mind, four modules times two CPU cores equals eight CPU cores.
So even AMD says it only has 2 cores. It looks more like a 4 core with 4 additional threads.

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post #15 of 166 (permalink) Old 08-27-2019, 04:22 PM
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Quote: Originally Posted by Diffident View Post
So even AMD says it only has 2 cores. It looks more like a 4 core with 4 additional threads.
You think one module is four threads? That would be silly, it only has two INT, one FPU and no SMT functionality.

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post #16 of 166 (permalink) Old 08-27-2019, 04:25 PM
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Seems a little silly to me. Sharing resources for more than one core could be good or bad. If you have 10Mbs of cache and two cores, it would be better if each core could use all 10 mbs rather than have two pools of 5mbs.

Seems like AMD could have beat this but probably settled because $12mil is nothing to them. Doesn't make sense to allow a group of random people to decided what they think a core is, and its a bad argument to say that this was misleading to anyone that would care. All you have to do is look at a benchmark to see what a CPU can do, it's not like the information was hidden. There are also a lot of games that use more than 4 cores that run great on bulldozer. BF4 was one of them, an FX-6300 was about on par with an i7 for that game.

It seems like by this logic, lots and lots of things could be considered false advertising.

Either way, 12 million dollars is a pretty small amount for a company like AMD and I doubt a lot of people will be trying to claim their $35 on such an old CPU.

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post #17 of 166 (permalink) Old 08-27-2019, 04:38 PM
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Quote: Originally Posted by KyadCK View Post
You think one module is four threads? That would be silly, it only has two INT, one FPU and no SMT functionality.
actually the FPU was modified to take on 2threads simultaneously.
so the FPU is technically doing SMT by default, this was also noted in wiki as "FlexFPU".

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post #18 of 166 (permalink) Old 08-27-2019, 04:45 PM
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Quote: Originally Posted by Seronx View Post
For example, if it was an actual criminal case they would have to prove beyond reasonable doubt that AMD didn't design two-cores.

A core would have seperate control units(thread/context manager), separate instruction buses, separate data buses, and separate execution datapaths.

Design of the Two-Core x86-64 AMD “Bulldozer” Module in 32 nm SOI CMOS;
"Each core is dedicated to a thread and contains a four-wide integer execution unit, issue/retire logic, 16KB four-way set associative L1 data cache, and a load/store unit."

Each core contains issue/retire logic => separate instruction buses. // Not something a single core would do, so not a single core.
Each core is dedicated to one of two threads => separate control units. // Not something a single core would do, so not a single core.
Each core has a data bus implied by the unshared L1d/LSU => separate data buses. // Not something a single core would do, so not a single core.
Each core has a four-wide integer datapath => seperate execution datapaths. // Not something a single core would do, so not a single core.

I have beyond reasonable doubt proven via published IEEE documents that AMD is innocent of false advertising. On any of the Zambezi, Vishera, Centurion SKUs selected for this lawsuit.
boy talk about moving the goal posts!

there are huge differences in criminal and civil law; you do not need to prove beyond any reasonable doubt, just what a reasonable mind could conclude.

what you're wanting is a smoking gun in the form of an internal memo that would specifically state the alleged deception. that, if it did ever exist, would certainly never be found.

since you know nothing of law given your post, let me happily inform you this is an agreement from both sides that either of them can lose the case.

if this is such a slam dunk as you say then:
https://regmedia.co.uk/2019/08/27/am...settlement.pdf
Spoiler!


they just needed published IEEE documents?

Remember the golden rule of statistics: A personal sample size of one is a sufficient basis upon which to draw universal conclusions.
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post #19 of 166 (permalink) Old 08-27-2019, 04:48 PM
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Quote: Originally Posted by epic1337 View Post
actually the FPU was modified to take on 2threads simultaneously.
so the FPU is technically doing SMT by default, this was also noted in wiki as "FlexFPU".
"The FP unit is fully dual-threaded and can issue and execute instructions from both threads simultaneously"
= Design of the Two-Core x86-64 AMD “Bulldozer” Module in 32 nm SOI CMOS

The front-end is a composite of SMT(Mostly) and CMP(Less);
-> The BTBs in Bulldozer are competitively shared by both cores, but provide greater coverage than the 2K entry BTB in Istanbul.
-> Bulldozer includes the familiar call/return stack, which is replicated per thread, rather than shared.
-> The IBB is the last stop before decoding and acts as the decoupling queue between fetch and decode. Accordingly, there are two IBBs, one dedicated per core.
-> The decoding begins by inspecting the first two of the 16B windows in the IBB for a single core.
-> After examining the instruction window, the decoders translate each x86 instruction into 1 or 2 macro-operations and place them into a queue for dispatching.
-> To accommodate both cores, Bulldozer’s decode stage has been widened.
= https://www.realworldtech.com/bulldozer

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post #20 of 166 (permalink) Old 08-27-2019, 04:50 PM
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Quote: Originally Posted by KyadCK View Post
You think one module is four threads? That would be silly, it only has two INT, one FPU and no SMT functionality.

No, as in a 4/8 thread cpu.



It has 4 modules so each module would be acting like 2 threads (1 core/ 1 thread), if everything on the module is shared between the 2 "cores" on the individual modules. This is just how it appears to me.

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