[TechSpot] Micron starts sampling DDR5 RDIMMs with industry partners - Page 2 - Overclock.net - An Overclocking Community
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[TechSpot] Micron starts sampling DDR5 RDIMMs with industry partners

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post #11 of 37 (permalink) Old 01-09-2020, 12:04 PM
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Quote: Originally Posted by epic1337 View Post
haha, in another forum i had mentioned adding more threads per core to maximize resource utilization and people thought it was a stupid idea, then came IBM's POWER8 processors.
8 threads per core, that makes AMD and Intel look like amateurs. Power9 is IBM's latest iteration and its impressive. I might even start a thread to discuss the Power9.
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post #12 of 37 (permalink) Old 01-09-2020, 12:07 PM
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Quote: Originally Posted by 8051 View Post
If the data still flows over the same CPU data bus for both DDR5 on-DIMM channels how can it be called a separate channel? I had thought separate memory channels had separate address/data lines so that you could perform read/writes to both channels simultaneously (i.e. to different memory addresses)?
according to tom's, the one i linked before, they split the DIMM module to have two independent 40bit channels.
the best thing however is it comes with an 8bit ECC for both read and write.

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The new DDR5 RAM standard also includes other new protocol features that are not related to the data rate transfers, but can still increase overall bandwidth.
For instance, DDR5 DIMMs will support two 40-bit (32-bit + ECC) independent channels.


The new default burst length of 16 (BL16) in DDR5 RAM allows a single burst to access 64B of data, which is the typical CPU cache line size, using only one of the two independent channels or half the DIMM.
This feature should provide a significant improvement in concurrency and effectively move us from the 8-channel memory systems we know today to a 16-channel system.

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post #13 of 37 (permalink) Old 01-09-2020, 03:20 PM
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Quote: Originally Posted by Ashura View Post
Mature DDR5 with high speed & relatively tighter timings would still be about a year from release/launch , right?
Depends on how close to the bleeding edge you mind being. One or another of the memory manufacturers will push to have high end ram available near the launch window.

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post #14 of 37 (permalink) Old 01-10-2020, 03:00 AM
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Quote: Originally Posted by epic1337 View Post
according to tom's, the one i linked before, they split the DIMM module to have two independent 40bit channels.
the best thing however is it comes with an 8bit ECC for both read and write.
So each channel provides 5 byte reads. Obviously CPU IMC's will have to change to work with that. This still doesn't address the issue of address lines, does each DDR5 channel have its own 64-bit address bus? If it doesn't, it would need to be time multiplexed and that wouldn't be as good as two separate memory channels.
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post #15 of 37 (permalink) Old 01-10-2020, 03:51 AM
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Quote: Originally Posted by speed_demon View Post
Depends on how close to the bleeding edge you mind being. One or another of the memory manufacturers will push to have high end ram available near the launch window.
yea, but that would come at quite a premium. For us regular users, 2022 or even 2023 might be the time to switch?

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post #16 of 37 (permalink) Old 01-10-2020, 03:58 AM
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Quote: Originally Posted by 8051 View Post
So each channel provides 5 byte reads. Obviously CPU IMC's will have to change to work with that. This still doesn't address the issue of address lines, does each DDR5 channel have its own 64-bit address bus? If it doesn't, it would need to be time multiplexed and that wouldn't be as good as two separate memory channels.
that one might be on what they changed in the Bus Inversion topology, they went from Data Bus Inversion (DBI) to Command/Address Inversion (CAI).

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post #17 of 37 (permalink) Old 01-10-2020, 01:31 PM
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Interesting. This is for the server space, hence why its all ECC.
Im sure we will get non-ECC variants for desktop use and clocked even higher.

Am i reading the bank groups correctly....dual-channel dims are going to be gone.
It looks like a minimum of 4 DIMMs.

Again this is for servers, so they may retain dual channel in the consumer space?

Im guessing Server ETA is mid-late 2020, making Consumer ETA mid to late 2021 and complete adoption in 2022(very limited (if any) new DDR4 products releasing).

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post #18 of 37 (permalink) Old 01-10-2020, 02:38 PM
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Quote: Originally Posted by SystemTech View Post
Interesting. This is for the server space, hence why its all ECC.
Im sure we will get non-ECC variants for desktop use and clocked even higher.
i hope not, ECC could actually help stabilize RAM at higher clocks, since minor errors can be corrected by ECC instead of outright crashing.
plus we're better off with ECC becoming a common feature, it might not be necessary for the mean time but with how fast capacities are growing preventing errors gets more necessary.

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post #19 of 37 (permalink) Old 01-11-2020, 12:48 AM
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Quote: Originally Posted by epic1337 View Post
i hope not, ECC could actually help stabilize RAM at higher clocks, since minor errors can be corrected by ECC instead of outright crashing.
plus we're better off with ECC becoming a common feature, it might not be necessary for the mean time but with how fast capacities are growing preventing errors gets more necessary.
ECC adds latency to every RAM access though, maybe with those higher speeds it won't matter.
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post #20 of 37 (permalink) Old 01-11-2020, 01:23 AM
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Lately we had DDR3,4 so what's on GPU's, isn't that DDR6, so what's that and why is only DDR5 upcoming on mainboards?

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