[TechSpot] Micron starts sampling DDR5 RDIMMs with industry partners - Page 3 - Overclock.net - An Overclocking Community
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[TechSpot] Micron starts sampling DDR5 RDIMMs with industry partners

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post #21 of 37 (permalink) Old 01-11-2020, 04:19 AM
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Quote: Originally Posted by 8051 View Post
ECC adds latency to every RAM access though, maybe with those higher speeds it won't matter.
yeah that was my thought, before we had like 800MT/s kits so ECC overhead was a huge penalty.
now a days we're going 3000MT/s all the way to 4000MT/s, with DDR5 proposing 6400MT/s kits, at these speeds losing like 10% hardly matters anymore.

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post #22 of 37 (permalink) Old 01-11-2020, 07:53 AM
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Quote: Originally Posted by 8051 View Post
If the data still flows over the same CPU data bus for both DDR5 on-DIMM channels how can it be called a separate channel? I had thought separate memory channels had separate address/data lines so that you could perform read/writes to both channels simultaneously (i.e. to different memory addresses)?
Quote: Originally Posted by 8051 View Post
So each channel provides 5 byte reads. Obviously CPU IMC's will have to change to work with that. This still doesn't address the issue of address lines, does each DDR5 channel have its own 64-bit address bus? If it doesn't, it would need to be time multiplexed and that wouldn't be as good as two separate memory channels.
It will not be the same data bus. Each RAM stick will have two 32-bit channels instead of one 64-bit channel. As you said, obviously the CPUs will change to support this.

Quote: Originally Posted by SystemTech View Post
Interesting. This is for the server space, hence why its all ECC.
Im sure we will get non-ECC variants for desktop use and clocked even higher.

Am i reading the bank groups correctly....dual-channel dims are going to be gone.
It looks like a minimum of 4 DIMMs.

Again this is for servers, so they may retain dual channel in the consumer space?

Im guessing Server ETA is mid-late 2020, making Consumer ETA mid to late 2021 and complete adoption in 2022(very limited (if any) new DDR4 products releasing).
You are reading it incorrectly. Each stick is now two 32-bit channels instead of one 64-bit one, so two DIMMS is quad-channel, four sticks is octo-channel, etc.

"Dual channel DDR5" would mean just one DIMM plugged into the system.

Quote: Originally Posted by Kaltenbrunner View Post
Lately we had DDR3,4 so what's on GPU's, isn't that DDR6, so what's that and why is only DDR5 upcoming on mainboards?
GPUs are using GDDR6, GDDR6X, and HBM.

They share most of a name, but they function differently. GPUs for example do not use "banks" or sticks, like CPUs do. Each die is 32-bit (for GDDR) and functions on it's own.

HBM is a whole other thing entirely.

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post #23 of 37 (permalink) Old 01-13-2020, 07:05 AM
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Quote: Originally Posted by KyadCK View Post
You are reading it incorrectly. Each stick is now two 32-bit channels instead of one 64-bit one, so two DIMMS is quad-channel, four sticks is octo-channel, etc.

"Dual channel DDR5" would mean just one DIMM plugged into the system.
Thank you. That is a interesting. Thanks for the reply

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post #24 of 37 (permalink) Old 01-13-2020, 07:04 PM
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Quote: Originally Posted by KyadCK View Post
It will not be the same data bus. Each RAM stick will have two 32-bit channels instead of one 64-bit channel. As you said, obviously the CPUs will change to support this.



You are reading it incorrectly. Each stick is now two 32-bit channels instead of one 64-bit one, so two DIMMS is quad-channel, four sticks is octo-channel, etc.

"Dual channel DDR5" would mean just one DIMM plugged into the system.



GPUs are using GDDR6, GDDR6X, and HBM.

They share most of a name, but they function differently. GPUs for example do not use "banks" or sticks, like CPUs do. Each die is 32-bit (for GDDR) and functions on it's own.

HBM is a whole other thing entirely.
OK I never looked it up, I just assumed it meant Graphic's DDR, well it still probably does, but yeah ok it's different

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post #25 of 37 (permalink) Old 01-16-2020, 01:53 PM
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Quote: Originally Posted by epic1337 View Post
that one might be on what they changed in the Bus Inversion topology, they went from Data Bus Inversion (DBI) to Command/Address Inversion (CAI).
But how are you going to send two different, unique physical addresses to two, independent memory channels at the same time over the same address lines? You can't have two separate address register output buffers driving the same line simultaneously?

Then you also need twice as many control lines for chip enables, RAS, CAS, WE etc. You can't be sharing control signals to independent memory channels if you're writing to one and reading from the other on the same DIMM -- or maybe that's disallowed (and so they're not fully independent memory channels)?
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post #26 of 37 (permalink) Old 01-16-2020, 03:13 PM
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Quote: Originally Posted by 8051 View Post
But how are you going to send two different, unique physical addresses to two, independent memory channels at the same time over the same address lines? You can't have two separate address register output buffers driving the same line simultaneously?

Then you also need twice as many control lines for chip enables, RAS, CAS, WE etc. You can't be sharing control signals to independent memory channels if you're writing to one and reading from the other on the same DIMM -- or maybe that's disallowed (and so they're not fully independent memory channels)?
from what i read so far they're treating DDR5 sticks as two physical DIMMs in one, so they actually have two separate lines.
they call it a subchannel in micron's page.

https://www.micron.com/products/dram/ddr5-sdram


edit: you can download micron's DDR5 white paper in that link at the bottom of the page.

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Last edited by epic1337; 01-16-2020 at 03:27 PM.
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post #27 of 37 (permalink) Old 01-17-2020, 05:40 AM
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Looks like according to that Micron page, where we used to have RAS, CAS, WE, etc command/address signals, DDR5 greatly reduces all those previously necessary connections

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post #28 of 37 (permalink) Old 01-19-2020, 05:53 AM
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Quote: Originally Posted by EniGma1987 View Post
Looks like according to that Micron page, where we used to have RAS, CAS, WE, etc command/address signals, DDR5 greatly reduces all those previously necessary connections
It looks to me like they're planning on time multiplexing address and command data over the same bus. While time multiplexing address data was already the standard w/DDR from the get-go the control signals all had independent pins. Low latency and a time-multiplexed bus work against each other.
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post #29 of 37 (permalink) Old 01-19-2020, 06:12 AM
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As long as you can get the clock high enough you can keep latencies the same. For some reason no one seems to want to decrease real memory latencies.

Edit: While I would like to see memory with lower real latencies, it is probably better to use the pins for extra lanes rather than control signals with today's high core count CPUs. Get the burst size and clocks up while increasing parallelism, more bandwidth for more threads at similar or only slightly worse real latencies. The second threads get much lower latencies since they do not need to wait for the first thread's burst to finish.

Last edited by Asmodian; 01-19-2020 at 06:31 AM.
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post #30 of 37 (permalink) Old 01-19-2020, 12:09 PM
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