Originally Posted by EniGma1987
Do we *know* they are multiplexing any of that though? Or just assume right now based on the info we see? Maybe they are not multiplexing anything and have two fully separate channels that can send/receive at the same time as each other.
DDR5 does in fact have more effective bandwidth per pin.
i'm quoting the white paper one more time...
Protocol Features for Performance
In addition to higher data rates and improvements to the I/O circuitry, DDR5 introduces other new protocol
features unrelated to data rate that are integral to increasing bandwidth and performance. For example, DDR5
DIMMs feature two 40-bit (32 bits plus ECC) independent channels. When combined with a new default burst
length of 16 (BL16) in the DDR5 component, this allows a single burst to access 64B of data (the typical CPU
cache line size) using only one of the independent channels, or only half of the DIMM. Providing this ability to
interleave accesses from these two independent channels enables tremendous improvements to concurrency,
essentially turning an 8-channel system as we know it today into a 16-channel system.
In the DRAM array, the number of bank groups (BGs) is doubling in DDR5 as compared to DDR4, keeping the
number of banks-per-BG the same, which effectively doubles the number of banks in the device. This enables
controllers to avoid the performance degradations associated with sequential memory accesses within the
same bank (for example, causing t CCD_S to be the sequential access restriction, instead of the much longer
t CCD_L). The addition of same-bank refreshes and improvements to the pre/postambles on the command bus
(by introducing an interamble) help to mitigate the traditional performance bottlenecks commonly observed in
DDR4, improving the overall effective bandwidth of the memory interface.
Data Burst Length Increase
DDR5 SDRAM default burst length increases from BL8 (seen on DDR4) to BL16 and improves command/address and
data bus efficiency. The same read or write CA bus transaction can now provide twice as much data on the data bus while
limiting the exposure to IO/array timing constraints within the same bank. Reducing the commands required to access a
given amount of data also improves the power profile for read and write accesses.
The burst length increase also reduces the number of IOs required to access the same 64B cache line data payload. The
default burst length increase enables a dual sub-channel for the DDR5 DIMM architecture (shown in Figure 2), which
increases overall channel concurrency, flexibility and count. For systems that utilize a 128B cache line data payload,
DDR5 adds a burst length of 32 option specifically for x4-configured devices. This further improves the command/address,
data bus efficiency and overall power profile.
in this case, they didn't multiplex it, they simply increased the command length to fit in more commands per pin.
trolling an adult is very dangerous, don't try it at home nor at work. you don't want to play tag with a rabid man.
Last edited by epic1337; 01-21-2020 at 04:29 PM.