[TechSpot] Micron starts sampling DDR5 RDIMMs with industry partners - Overclock.net - An Overclocking Community
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[TechSpot] Micron starts sampling DDR5 RDIMMs with industry partners

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post #1 of 37 (permalink) Old 01-08-2020, 01:19 AM - Thread Starter
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[TechSpot] Micron starts sampling DDR5 RDIMMs with industry partners

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Micron at CES this week announced it has begun sampling DDR5 registered DIMMS (RDIMM) based on its 1znm process technology. According to the memory maker, its new DDR5 – which doubles memory density while improving reliability – will deliver more than an 85 percent increase in memory performance among server workloads.

DDR5 also affords lower power requirements, making it more energy efficient at scale, and features enhancements like MIR (“mirror” pin) that improves DIMM signaling. There are also more options for PRECHARGE and REFRESH commands, we’re told.


Source: https://www.techspot.com/news/83440-...-partners.html

My guess is we will start seeing this around 2022.

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post #2 of 37 (permalink) Old 01-08-2020, 02:07 AM
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they all come with ECC? thats fantastic news, with the ever increasing capacity ECC should become more necessary than ever to prevent random data corruptions.

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post #3 of 37 (permalink) Old 01-08-2020, 09:57 AM
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am5 2021 then?

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post #4 of 37 (permalink) Old 01-08-2020, 10:06 AM
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DDR5-3200 provides 1.36x higher bandwidth compared to DDR4-3200

https://images.anandtech.com/doci/15...st_image_2.PNG
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post #5 of 37 (permalink) Old 01-08-2020, 11:59 AM
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https://www.tomshardware.com/news/wh...ram,39079.html

could add this to OP, a more thorough introduction to DDR5.

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post #6 of 37 (permalink) Old 01-08-2020, 12:15 PM
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Quote:
The new DDR5 RAM standard also includes other new protocol features that are not related to the data rate transfers, but can still increase overall bandwidth. For instance, DDR5 DIMMs will support two 40-bit (32-bit + ECC) independent channels.The new default burst length of 16 (BL16) in DDR5 RAM allows a single burst to access 64B of data, which is the typical CPU cache line size, using only one of the two independent channels or half the DIMM. This feature should provide a significant improvement in concurrency and effectively move us from the 8-channel memory systems we know today to a 16-channel system.
Sweet. This is something I brought up a long time ago as a way of getting more channels in system RAM per slot on the MB. It was fun having people laugh at such a suggestion 2 years ago and say it will never happens and cant be done in DDR type memory

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post #7 of 37 (permalink) Old 01-08-2020, 12:27 PM
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Quote: Originally Posted by EniGma1987 View Post
Sweet. This is something I brought up a long time ago as a way of getting more channels in system RAM per slot on the MB. It was fun having people laugh at such a suggestion 2 years ago and say it will never happens and cant be done in DDR type memory
haha, in another forum i had mentioned adding more threads per core to maximize resource utilization and people thought it was a stupid idea, then came IBM's POWER8 processors.

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post #8 of 37 (permalink) Old 01-09-2020, 01:00 AM
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Mature DDR5 with high speed & relatively tighter timings would still be about a year from release/launch , right?

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post #9 of 37 (permalink) Old 01-09-2020, 03:29 AM
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Quote: Originally Posted by Ashura View Post
Mature DDR5 with high speed & relatively tighter timings would still be about a year from release/launch , right?
It will take DDR5 at least two years to yield results that make it worthwhile to switch from DDR4. If you go back to the very first reviews of DDR4 you will find there was no difference between DDR3 and 4, and at times there was even a regression due to timing increase. But once DDR4 3000 was released there was a (somewhat) tangible difference. However, there will be no noticeable difference between either for regular users, as the bandwidth will mostly be beneficial to servers. Desktop machinese are rarely ever bandwidth limited and more CPU or GPU limited, depending on the scenario.

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post #10 of 37 (permalink) Old 01-09-2020, 11:58 AM
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Quote: Originally Posted by EniGma1987 View Post
Sweet. This is something I brought up a long time ago as a way of getting more channels in system RAM per slot on the MB. It was fun having people laugh at such a suggestion 2 years ago and say it will never happens and cant be done in DDR type memory
If the data still flows over the same CPU data bus for both DDR5 on-DIMM channels how can it be called a separate channel? I had thought separate memory channels had separate address/data lines so that you could perform read/writes to both channels simultaneously (i.e. to different memory addresses)?
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