[WCCFTech] NVIDIA Ditches Intel Xeon, Goes All Onboard With AMD’s EPYC CPUs With Next-Gen Ampere GPUs - Overclock.net - An Overclocking Community
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[WCCFTech] NVIDIA Ditches Intel Xeon, Goes All Onboard With AMD’s EPYC CPUs With Next-Gen Ampere GPUs

 
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post #1 of 6 (permalink) Old 05-14-2020, 06:46 AM - Thread Starter
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[WCCFTech] NVIDIA Ditches Intel Xeon, Goes All Onboard With AMD’s EPYC CPUs With Next-Gen Ampere GPUs

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In a surprise unveil, NVIDIA has decided to ditch Intel's Xeon CPUs and go all onboard with AMD's EPYC Rome processors to power its next-generation Ampere GPU powered DGX systems. This will be the first full outing of two next-generation 7nm server products in the same platform featuring insane hardware specifications.


The news announcement comes on the launch of NVIDIA's Ampere GPU which is by far the biggest 7nm GPU ever built. In the presser, NVIDIA revealed full technical specifications of its latest DGX-A100 system that will be utilizing NVIDIA's 7nm Ampere GPUs and AMD's 7nm EPYC Rome CPUs, marking the first time that green team has opted for AMD's server chips for use in its flagship HPC platform.
https://wccftech.com/nvidia-ditches-...n-ampere-gpus/

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post #2 of 6 (permalink) Old 05-14-2020, 06:58 AM
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They would be dumb to not choose 2nd gen EPYC. The density is insane, over twice as much cores in the same amount of servers.

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post #3 of 6 (permalink) Old 05-14-2020, 07:02 AM
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Quote: Originally Posted by ku4eto View Post
They would be dumb to not choose 2nd gen EPYC. The density is insane, over twice as much cores in the same amount of servers.
They are using rome, which is 2nd gen. Milan will only come late 2020, which means 2021 actual usage.
Going to 9282 will mean losing just 16 cores, but the problem will be power and heat (as the 9282 is 400w vs 280w), as well as PCIE lanes which will affect their interconnections capability.
I'm actually more surprised they didn't use a power 9, as IBM has support for nvlink which could increase internal communication over using extra nvlink switches. But maybe it works out better.



Last edited by Defoler; 05-14-2020 at 07:08 AM.
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post #4 of 6 (permalink) Old 05-14-2020, 07:09 AM
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Quote: Originally Posted by Defoler View Post
They are using rome, which is 2nd gen. Milan will only come late 2020, which means 2021 actual usage.
Going to 9282 will mean losing just 16 cores, but the problem will be power and heat (as the 9282 is 400w vs 280w), as well as PCIE lanes which will affect their interconnections capability.
I'm actually more surprised they didn't use a power 9, as IBM has support for nvlink which could increase internal communication over using extra nvlink switches. But maybe it works out better.
The price of the POWER is insane. As well as the support.

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post #5 of 6 (permalink) Old 05-14-2020, 07:14 AM
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It's right there in the keynote.


Starting around min 12.
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post #6 of 6 (permalink) Old 05-14-2020, 07:58 AM
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Quote: Originally Posted by ku4eto View Post
The price of the POWER is insane. As well as the support.
I'm not sure sure. The 64 core roma cpus start at just over 6000$ price tag, while the S922 (power 9 22 core SMT4) cost about 3200$, and with SMT4 you get 80 threads chip running linux, or 160 with 2 processors. And they come with direct CPU nvlink.
I expect top 7H12 and S924 will basically cost the same. And you get 256 threads vs 192 threads, but you also gain nvlink. But I guess 7nm and lower power were also important.
So it depends on the roma cpu model they will be using. The mid power 9 chips are extremely cost efficient and nvidia have a decent history with ibm.


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