Originally Posted by WannaBeOCer
It's no surprise Alder Lake doesn't have AVX-512. Lakefield also doesn't have any AVX instructions even though they have 1 sunny cove core. Ice Lake(Sunny Cove cores) and Tiger Lake(Willow Cove cores) support AVX-512. We won't see AVX-512 on the mainstream chipsets until they release their next generation architecture in 2022.
This right here demonstrates the problem with AVX-512. Intel - on their own product information pages - fail to explain which subsets of AVX-512 a given "AVX-512" chip supports. The fact that there are subsets in the first place is problematic. Is it the baseline/minimum AVX-512 extensions (the so called "F" extentions)? Or the CD, ER, PF, VL, DQ, BW, IFMA, VBMI, 4VNNIW, 4FMAPS, VPOPCNTDQ, VNNI, WBMI2, BITALG or VP2INTERSECT parts of AVX-512... or a selection of the above?
For example, the only AVX-512 CPU I have access to supports F, CD, BW, VL and DQ. But I have to go to a system information utility or wikichip to identify that, because Intel seem to hide easy access to the AVX-512 subsets supported on their various AVX-512 CPUs on the Ark.
Intel also say AVX-512 has entered the consumer CPU space with Cannon Lake... but that appears to be a single i3 CPU, with succeeding CPUs (including Comet Lake/10900K etc) not
having AVX-512. Why did they bother releasing a mobile i3 CPU with AVX-512? The only conclusion I can come to basically is marketing, as a dual-core, low-TDP, RAM-limited CPU is hardly a good testbed for the kind of HPC crunching that AVX-512 was dreamed up for.
AVX-512 has always been a mess, largely due to the abject failure that was the Xeon Phi, which "premiered" AVX-512. I'm left with the impression - whether rightly or wrongly - that AVX-512 was a bit of a bodge/hack attempt to get the Phi to crunch data at the same sort of speeds as GPUs were capable. When the Phi failed, Intel were left with an extension set and a need to get something - anything - in return for their R&D expenditures. The difficulties they've had with 10nm haven't helped, either, but don't explain the fragmentation of the AVX-512 instruction set.