[Tom's Hardware] Linus Torvalds Wishes Intel's AVX-512 A Painful Death - Page 2 - Overclock.net - An Overclocking Community

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[Tom's Hardware] Linus Torvalds Wishes Intel's AVX-512 A Painful Death

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post #11 of 33 (permalink) Old 07-12-2020, 10:00 PM
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Quote: Originally Posted by WannaBeOCer View Post
It's no surprise Alder Lake doesn't have AVX-512. Lakefield also doesn't have any AVX instructions even though they have 1 sunny cove core. Ice Lake(Sunny Cove cores) and Tiger Lake(Willow Cove cores) support AVX-512. We won't see AVX-512 on the mainstream chipsets until they release their next generation architecture in 2022.

https://ark.intel.com/content/www/us...-3-90-ghz.html
This right here demonstrates the problem with AVX-512. Intel - on their own product information pages - fail to explain which subsets of AVX-512 a given "AVX-512" chip supports. The fact that there are subsets in the first place is problematic. Is it the baseline/minimum AVX-512 extensions (the so called "F" extentions)? Or the CD, ER, PF, VL, DQ, BW, IFMA, VBMI, 4VNNIW, 4FMAPS, VPOPCNTDQ, VNNI, WBMI2, BITALG or VP2INTERSECT parts of AVX-512... or a selection of the above?

For example, the only AVX-512 CPU I have access to supports F, CD, BW, VL and DQ. But I have to go to a system information utility or wikichip to identify that, because Intel seem to hide easy access to the AVX-512 subsets supported on their various AVX-512 CPUs on the Ark.

Intel also say AVX-512 has entered the consumer CPU space with Cannon Lake... but that appears to be a single i3 CPU, with succeeding CPUs (including Comet Lake/10900K etc) not having AVX-512. Why did they bother releasing a mobile i3 CPU with AVX-512? The only conclusion I can come to basically is marketing, as a dual-core, low-TDP, RAM-limited CPU is hardly a good testbed for the kind of HPC crunching that AVX-512 was dreamed up for.

AVX-512 has always been a mess, largely due to the abject failure that was the Xeon Phi, which "premiered" AVX-512. I'm left with the impression - whether rightly or wrongly - that AVX-512 was a bit of a bodge/hack attempt to get the Phi to crunch data at the same sort of speeds as GPUs were capable. When the Phi failed, Intel were left with an extension set and a need to get something - anything - in return for their R&D expenditures. The difficulties they've had with 10nm haven't helped, either, but don't explain the fragmentation of the AVX-512 instruction set.


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post #12 of 33 (permalink) Old 07-12-2020, 10:50 PM - Thread Starter
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Quote: Originally Posted by Paradigm Shifter View Post
This right here demonstrates the problem with AVX-512. Intel - on their own product information pages - fail to explain which subsets of AVX-512 a given "AVX-512" chip supports. The fact that there are subsets in the first place is problematic. Is it the baseline/minimum AVX-512 extensions (the so called "F" extentions)? Or the CD, ER, PF, VL, DQ, BW, IFMA, VBMI, 4VNNIW, 4FMAPS, VPOPCNTDQ, VNNI, WBMI2, BITALG or VP2INTERSECT parts of AVX-512... or a selection of the above?

For example, the only AVX-512 CPU I have access to supports F, CD, BW, VL and DQ. But I have to go to a system information utility or wikichip to identify that, because Intel seem to hide easy access to the AVX-512 subsets supported on their various AVX-512 CPUs on the Ark.

Intel also say AVX-512 has entered the consumer CPU space with Cannon Lake... but that appears to be a single i3 CPU, with succeeding CPUs (including Comet Lake/10900K etc) not having AVX-512. Why did they bother releasing a mobile i3 CPU with AVX-512? The only conclusion I can come to basically is marketing, as a dual-core, low-TDP, RAM-limited CPU is hardly a good testbed for the kind of HPC crunching that AVX-512 was dreamed up for.

AVX-512 has always been a mess, largely due to the abject failure that was the Xeon Phi, which "premiered" AVX-512. I'm left with the impression - whether rightly or wrongly - that AVX-512 was a bit of a bodge/hack attempt to get the Phi to crunch data at the same sort of speeds as GPUs were capable. When the Phi failed, Intel were left with an extension set and a need to get something - anything - in return for their R&D expenditures. The difficulties they've had with 10nm haven't helped, either, but don't explain the fragmentation of the AVX-512 instruction set.
Found it instantly on their site using their search. Cooper Lake is looking very exciting. It also added bfloat16 just like nVidia's new Tensor cores and AMD's next generation CDNA. They also improved training performance and inferencing by 60% compared to Cascade Lake.

https://software.intel.com/content/w...9s%20%20Manual

General:
AVX512F
AVX512CD

Skylake SP:
AVX512BW
AVX512DQ
AVX512VL

Cannon Lake:
AVX512VBMI
AVX512IFMA

Cascade Lake:
AVX512_VNNI

Cooper Lake:
AVX512_BF16

Ice Lake added:
AVX512_VPOPCNTDQ
AVX512_VNNI
AVX512_VBMI2
AVX512_BITALG
AVX512+VAES
AVX512+GFNI
AVX512+VPCLMULQDQ

Tiger Lake:
AVX512_VP2INTERSECT

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post #13 of 33 (permalink) Old 07-12-2020, 10:57 PM
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Quote: Originally Posted by WannaBeOCer View Post
Found it instantly on their site using their search. Cooper Lake is looking very exciting. It also added bfloat16 just like nVidia's new Tensor cores and AMD's next generation CDNA. They also improved training performance and inferencing by 60% compared to Cascade Lake.

https://software.intel.com/sites/def...-reference.pdf

https://www.intel.com/content/www/us...t&t=Developers
Yes, well done, but you missed the point. It is on their site in the developer documentation - I would hope they would provide information for devs about their instruction sets!

But they do not make it clear in the Ark. And it still does not solve the issue with fragmentation of the AVX-512 instruction set.


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post #14 of 33 (permalink) Old 07-12-2020, 11:45 PM
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Quote: Originally Posted by WannaBeOCer View Post
Edit: His argument is related to Intel segmenting their chips with AVX-512. I'm sure regular consumers would rather pay less to not have hardware and an instruction set that won't they be using than paying more for it. Take Nvidia's Tensor cores for example.
Putting it inside their "regular" chips has two reasons.

One, it saves money not having to create two different architectures, one with and one without. They already have so many variations of chips, adding more is just more complicated, and it makes the consumers confused what chip they actually need. If someone who uses programs that use avx-512 for example playing around with maya, autocard, etc on his gaming machine, suddenly realizing it slows down because avx-512 is gone and he needed to get another chip, it gets confusing.

Second, it helps them in a leg up over AMD in some use cases.
If you use avx-512 extensions (which some reviews don't), you suddenly get a better performing system even though it has less cores than AMD. This helps intel sell to both enterprise and end consumers. AMD can push things through brute force because of higher core count, and sometimes it isn't enough.
So just like RTX, even if you are not using ray tracing, it helps nvidia sell GPUs.

Besides, it is not like intel are the only ones doing it. AMD ryzen also have instructions and functionality you aren't going to use. But in order to save money, they make the chiplets basically similar, so it saves them a lot of money to just more the same chiplets, and handle it through firmware, even if it adds up a bit per chip, overall, the cost is mute compared to the savings.


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post #15 of 33 (permalink) Old 07-13-2020, 03:40 AM
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Quote: Originally Posted by 8051 View Post
Here's a different opinion of AVX-512 (from: https://www.prowesscorp.com/what-is-...oes-it-matter/). Just because it's useless to Linus Torvalds doesn't mean other people can't find a use for them.

Intel AVX-512 can accelerate performance for workloads and use cases such as scientific simulations, financial analytics, artificial intelligence (AI)/deep learning, 3D modeling and analysis, image and audio/video processing, cryptography, and data compression.
And how many of those very tasks can be done even faster on GPUs?

And those use cases are quite niche, putting AVX512 in half your product stack is only wasting transistor space and increasing costs to customers for little to no benefit.

Quote: Originally Posted by Defoler View Post
Besides, it is not like intel are the only ones doing it. AMD ryzen also have instructions and functionality you aren't going to use. But in order to save money, they make the chiplets basically similar, so it saves them a lot of money to just more the same chiplets, and handle it through firmware, even if it adds up a bit per chip, overall, the cost is mute compared to the savings.
Name one instruction set / function inside a Ryzen CPU that is comparable to the transistor and die space taken up by AVX512 that has anywhere near as limited usage cases?

I don't think you realize how much AVX512 demands.

And I doubt it would be cheaper. As Intel have multiple implementations of AVX512... depending on what CPU you buy certain capabilities are and are not present of the AVX512 instruction set. Which kinda contradicts your whole argument there.



Last edited by matthew87; 07-13-2020 at 03:53 AM.
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post #16 of 33 (permalink) Old 07-13-2020, 03:45 AM
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Quote: Originally Posted by 8051 View Post
Here's a different opinion of AVX-512 (from: https://www.prowesscorp.com/what-is-...oes-it-matter/). Just because it's useless to Linus Torvalds doesn't mean other people can't find a use for them.

Intel AVX-512 can accelerate performance for workloads and use cases such as scientific simulations, financial analytics, artificial intelligence (AI)/deep learning, 3D modeling and analysis, image and audio/video processing, cryptography, and data compression.

Intel AVX-512 can also help data centers more efficiently use available storage resources. Simply put, it accelerates storage functions, such as deduplication, encryption, compression, and decompression. It accomplishes this by doubling the number of bits in the register from 256 to 512 (see an illustrative animation here). In fact, it calculates storage functions in half the time of the previous generation.

This acceleration has a number of use cases:

63 times faster high-performance computing*
2 times faster AI/deep learning*
1 times faster cryptographic hashing performance*
2 times faster data protection*

This exceptional processing of encryption algorithms helps reduce the performance overhead for cryptography, which means you can deploy more secure data and services into distributed environments without compromising performance.
And then mitigations were applied and performance was so good that people turned to ARM and AMD for their super computers.

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post #17 of 33 (permalink) Old 07-13-2020, 06:34 AM
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Quote: Originally Posted by skupples View Post
the creator of linux has a strong opinion about something?


shocking, truly.
I see n1 **** poster on here gg.

Linus is right once again and he's not afraid to say it.

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post #18 of 33 (permalink) Old 07-13-2020, 06:38 AM
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Quote: Originally Posted by oskullop View Post
n1 **** poster on here.
Torvalds definitely doesn't post here, if he did he'd get banned within minutes.

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Haha, Liranan, you creep.

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post #19 of 33 (permalink) Old 07-13-2020, 06:42 AM
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Quote: Originally Posted by 8051 View Post
Intel AVX-512 can also help data centers more efficiently use available storage resources. Simply put, it accelerates storage functions, such as deduplication, encryption, compression, and decompression. It accomplishes this by doubling the number of bits in the register from 256 to 512 (see an illustrative animation here). In fact, it calculates storage functions in half the time of the previous generation.

This acceleration has a number of use cases:

63 times faster high-performance computing*
2 times faster AI/deep learning*
1 times faster cryptographic hashing performance*
2 times faster data protection*

This exceptional processing of encryption algorithms helps reduce the performance overhead for cryptography, which means you can deploy more secure data and services into distributed environments without compromising performance.

You mean all the things offloaded to server NICs since one of the very most important things for data centers and financial markets is freeing up CPU cycles?

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post #20 of 33 (permalink) Old 07-13-2020, 07:39 AM
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So let me understand this, RISCV Vector extension > AVX-512 but Intel doesn't own RISCV Vector extension so they are pushing AVX-512 instead?

Sounds about right.




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Last edited by Hueristic; 07-13-2020 at 07:42 AM.
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