[ANANDTECH] DDR5 Memory Specification Released: Setting the Stage for DDR5-6400 And Beyond - Overclock.net - An Overclocking Community

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[ANANDTECH] DDR5 Memory Specification Released: Setting the Stage for DDR5-6400 And Beyond

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post #1 of 22 (permalink) Old 07-14-2020, 02:14 PM - Thread Starter
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[ANANDTECH] DDR5 Memory Specification Released: Setting the Stage for DDR5-6400 And Beyond

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Marking an important milestone in computer memory development, today the JEDEC Solid State Technology Association is releasing the final specification for its next mainstream memory standard, DDR5 SDRAM. The latest iteration of the DDR standard that has been driving PCs, servers, and everything in-between since the late 90s, DDR5 once again extends the capabilities of DDR memory, doubling the peak memory speeds while greatly increasing memory sizes as well. Hardware based on the new standard is expected in 2021, with adoption starting at the sever level before trickling down to client PCs and other devices later on.


Originally planned for release in 2018, today’s release of the DDR5 specification puts things a bit behind JEDEC’s original schedule, but it doesn’t diminish the importance of the new memory specification. Like every iteration of DDR before it, the primary focus for DDR5 is once again on improving memory density as well as speeds. JEDEC is looking to double both, with maximum memory speeds set to reach at least 6.4Gbps while the capacity for a single, packed-to-the-rafters LRDIMM will eventually be able to reach 2TB. All the while, there are several smaller changes to either support these goals or to simplify certain aspects of the ecosystem, such as on-DIMM voltage regulators as well as on-die ECC.

https://www.anandtech.com/show/15912...400-and-beyond
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post #2 of 22 (permalink) Old 07-14-2020, 02:56 PM
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Looking forward to this. Thought we would have DDR5 a bit sooner, but better late than never. Have planned an upgrade once it comes out.

I am betting that we will see 10000mhz DDR for the first time, since there was a post/news here on OCN which said DDR5 was already at 8600mhz or something like that. Exciting!

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post #3 of 22 (permalink) Old 07-14-2020, 03:46 PM
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So is all DDR5 ram going to be ECC?

Sounds like DDR5 is too far out to wait for an upgrade for me.

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post #4 of 22 (permalink) Old 07-14-2020, 04:09 PM
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Quote: Originally Posted by go4life View Post
Looking forward to this. Thought we would have DDR5 a bit sooner, but better late than never. Have planned an upgrade once it comes out.

I am betting that we will see 10000mhz DDR for the first time, since there was a post/news here on OCN which said DDR5 was already at 8600mhz or something like that. Exciting!
"10000mhz", aka 5GHz DDR, aka still on the same old 200mhz internal memory clock still.
Wonder when they will stop just increasing prefetch each generation and actually get a clock speed bump. Then we could actually get higher speed without having to go a lot higher again on the column strobe latency. If all they want to continue to do is double the prefetch each time then jedec should just jump to 128n now and stop wasting everyones time.


edit: Ha. Well at least Anand writers arent completely stupid either and at least tried to point out the elephant in the room:
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The big challenge as always for DRAM speeds, comes from the lack of progress in DRAM core clock rates. Dedicated logic is still getting faster, and memory busses are still getting faster, but the capacitor-and-transistor-based DRAM underpinning modern memory still can’t clock higher than a few hundred megahertz.


Last edited by EniGma1987; 07-14-2020 at 04:13 PM.
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post #5 of 22 (permalink) Old 07-14-2020, 04:40 PM
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Quote: Originally Posted by EniGma1987 View Post
"10000mhz", aka 5GHz DDR, aka still on the same old 200mhz internal memory clock still.
Wonder when they will stop just increasing prefetch each generation and actually get a clock speed bump. Then we could actually get higher speed without having to go a lot higher again on the column strobe latency. If all they want to continue to do is double the prefetch each time then jedec should just jump to 128n now and stop wasting everyones time.


edit: Ha. Well at least Anand writers arent completely stupid either and at least tried to point out the elephant in the room:
Can you explain why that would matter? Does it make a performance difference in the end?

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post #6 of 22 (permalink) Old 07-14-2020, 07:08 PM
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Quote: Originally Posted by UltraMega View Post
Can you explain why that would matter?
+1

I want to avoid a google rabbit hole on this, unless someone has a relevant article handy discussing this.

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post #7 of 22 (permalink) Old 07-14-2020, 08:55 PM
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Quote: Originally Posted by UltraMega View Post
Can you explain why that would matter? Does it make a performance difference in the end?
As we keep going up in the speed of the external interface without raising the internal clock of the memory itself we also have to go up in CAS timings. These timings are how many clock cycles pass between providing the memory address and then receiving the data. They go up as the external interface goes up but internal clock doesnt. If DDR5 were to actually raise the internal memory clock, then we would actually be able to make a jump in speed to things like "DDR-6400" without doubling the CAS timings like we have every generation.

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post #8 of 22 (permalink) Old 07-14-2020, 09:26 PM
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Will this mean more RGB ram? Twice the amount of RGB on one stick?
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post #9 of 22 (permalink) Old 07-14-2020, 11:16 PM
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Quote: Originally Posted by EniGma1987 View Post
As we keep going up in the speed of the external interface without raising the internal clock of the memory itself we also have to go up in CAS timings. These timings are how many clock cycles pass between providing the memory address and then receiving the data. They go up as the external interface goes up but internal clock doesnt. If DDR5 were to actually raise the internal memory clock, then we would actually be able to make a jump in speed to things like "DDR-6400" without doubling the CAS timings like we have every generation.
Interesting. Is there a easy to understand reason why it's difficult to increase the internal clock?

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post #10 of 22 (permalink) Old 07-15-2020, 12:57 AM
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Quote: Originally Posted by UltraMega View Post
Interesting. Is there a easy to understand reason why it's difficult to increase the internal clock?
it has something to do with how the memory cells handles charge-discharge cycles.
the way they had bypassed this is charging more cells in parallel (more bits per cycle).

SRAM would be superior to DRAM in this case, but it has it's own disadvantages.

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