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post #3757 of (permalink) Old 01-25-2017, 11:43 AM
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Quote:
Originally Posted by tknight View Post

Where did you get that formula for tRAS ?

This diagram shows the RAS line held low until tRCD, CAS, and at least 2 clocks of data have been output. If the RAS line goes high before that, you're asking the memory controller to unlatch the row before you've got the requested data from it.

http://www.electronics.dit.ie/staff/tscarff/memory/DRAM_READ_CYCLE.jpg

What hangs in the balance at the board level - not the chipset level - is how the number of clocks you've entered for tRAS is interpreted. Most of the time, it should be a 1:1 relationship. Any timing set below the minimum "electrical" value is simply substituted so that the operation can be performed. The penalty of this is unknown, but there's usually a drop in performance at a certain point. Indirect realtionships to other timings can play a part in perceived performance gains (in this case it would likely be from tRC). Make no mistake that the law is real, it's just the interface layer that is sometimes fuzzy.

-Raja

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