Originally Posted by The Stilt
The memory controller FW used in 184.108.40.206 still has room for improvements.
If the CLDO_VDDP is out of whack then it will fail memory training all together. I've yet to see any kind of improvement in stability from VDDP adjustment.
I'm not sure what the programming rules for tCWL are in this specific version, but make sure it is in sync with tCL on dual rank modules. Also if you're running high VDDCR_SoC voltages, try lowering it a bit (< 1.100V). Other than that there is not much you can do about it.
Thanks, tCWL seems to okay (equal to tCL). tFAW is 33 on auto, but the XMP profile recommends 39. With lower SOC voltage, I usually get more errors, not less. 1.10v has more errors than 1.18v