What I have collated so far from posts, etc.Warning: Spoiler! (Click to show)
tCL if odd will need GearDown to be disabled, otherwise it is rounded to even number.
tRCDWR match with tCL and lower as much as you can.
tRCDRD match with tCL and lower as much as you can.
tRP match with tCL and lower as much as you can.
tRAS = tCL + tRCD + tRTP (See note 1)
tRC = tRAS + tRP (See note 1)
tFAW = 4x tRTP (See note 1)
tFAWDLR and tFAWSLR should be 0.
tRCPage should be 0.
tRDRDSCL set as 2.
tWRWRSCL set as 2.
tRFC AFAIK has no rule, tRFC 2 and 4 ignore and leave on [Auto], guidance from The Stilt C6H thread.
tCWL match to tCL, if tCL is odd then select -1 from it to be even value. Odd tCWL does not apply when I have tried.
tWRWRSC set as 1.
tWRWRSD and tWRWRDD match to each other, from having seen The Stilt's tightest profile
for 3466MHz (not in UEFI presets), 7 would the number.
tRDRDSC set as 1.
tRDRDSD and tRDRDD match to each other, from having seen The Stilt's tightest profile
for 3466MHz (not in UEFI presets), 5 would the number.
tCKE ??? (Post by The Stilt and [email protected]
in C6H thread)
Note 1: It being looser than calc can aid stability.
Link to post
by The Stilt on critical timings on Ryzen, which I believe would be same case for ThreadRipper.
Been busy with other things to finish it. If members know/have answers for ??? values I will place completed info in OP
. Also if there are errors/suggestions people wish to make on what I collated please feel free to post and can amend