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post #220 of (permalink) Old 04-24-2018, 09:15 AM
The Stilt
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Quote: Originally Posted by asdkj1740 View Post
some users report the pe4 would boost the voltage to >1.55v which is siad to be unsafe for the long run.
i just want to maximize the single core performance for gaming purpose, but i found that when single core is boosted to 4.4g~4.5g, the rest were just <3ghz....any suggestion to raise those rest cores frequecenies while having highest single core frequencies at the same time??

thanks i will try pe4 tmr
This is what I wrote few days ago:

The maximum safe voltages for CPUs are an eternal riddle, as neither of the two manufacturers release this information for public consumption. Public or even the NDA documents generally specify a vague limit, which most of the time relates to a point where the catastrophic failures become more common instead of specifying the voltage that is safe to sustain without causing any damage to the silicon. Such limit is admittingly rather hard to specify, as the limit will vary between the different CPU specimens (silicon variance, SIDD) and operating scenarios (peak current in different utilization scenarios, temperature, etc.).

In order to get the most accurate answer for this question I ended up “asking” the CPU itself. As stated previously, the CPU features various different limiters / safe guards (Package Power Tracking: PPT, Thermal Design Current: TDC, Electrical Design Current: EDC, thermal protection and FIT).

“FIT” as the name suggest is a feature to monitor / track the fitness of the silicon and adjust the operating parameters to maintain the specified and expected reliability. Many semiconductor manufacturers utilize such feature to eke out every last bit of performance, in an ERA where most of the semiconductors are process bound in terms of performance. In short: FIT feature allows the manufacturers to push their designs to the very limit out of the box, without jeopardizing the reliability of the silicon. A practical example would be the knock sensors on an engine. The control unit of the engine always tries to advance the ignition timing as much as possible, to produce the best possible power / torque figures. The purpose of the knock sensors is to listen if knocking occurs and tell the ECU to reduce the timing advance when it does, in order to protect the engine.

To see what the actual maximum voltage FIT allows the CPU to run at in various different scenarios is, I disabled all of the other limiters and safe guards. With every other limiter / safe guard disabled, the reliability (FIT) becomes the only restrain. The voltage command which the CPU sends to the VRM regulator via the SVI2 interface and the actual effective voltage were then recorded in various scenarios. In stock configuration the sustained maximum effective voltage during all-core stress allowed by FIT was =< 1.330V. Meanwhile, in single core workloads the sustained maximum was =< 1.425V. When the “FIT” parameters were adjusted by increasing the scalar value from the default 1x to the maximum allowed value of 10x, the maximum all-core voltage became 1.380V, while the maximum single core voltage increased to 1.480V. The recorded figures appear to fall very well in line with the seen and known behavior, frequency, power and thermal scaling wise.

The seen behavior suggests that the full silicon reliability can be maintained up to around 1.330V in all-core workloads (i.e. high current) and up to 1.425V in single core workloads (i.e. low current). Use of higher voltages is definitely possible (as FIT will allow up to 1.380V / 1.480V when scalar is increased by 10x), but it more than likely results in reduced silicon lifetime / reliability. By how much? Only the good folks at AMD who have access to the simulation data will know for sure.

These figures will almost certainly vary between the different CPU specimens (due to SIDD and other silicon specific factors), however the recorded values were almost identical on all of the tested samples (within 20mV, lowest-highest leaking specimen).

Also note that the figures stated here relate to the actual effective voltage, and not to the voltage requested by the CPU. The CPU is aware of the actual effective voltage, so things like load-line adjustments and voltage offsets will modify the CPUs voltage request from the VRM controller accordingly. The most accurate method to measure the effective voltage on AM4 platform is to monitor the “VDDCR_CPU SVI2 TFN” voltage, which is available in HWInfo. This reading is sourced directly from the VRM controller (through SVI2 interface) and generally it is the most accurate reading available to end-users by far. As a side note, while the TFN (“telemetry function”) voltage readings are always generic (and accurate), never blindly trust the reported current and power readings (as every motherboard model needs separate calibration).
The voltage requests you are seeing are irrelevant, only the actual voltage matters.
Look at the TFN voltage figure and nothing else.

The voltage will vary depending on several things. In single threaded workloads it varies heavily based on the core the workload is being scheduled on.

Here's some figures with PE3:

ST workload scheduled on the best core of the CPU (Core 2):


Peak voltage 1.451V, while the average being 1.372V.

ST workload scheduled on the worst core of the CPU (Core 7):


Peak voltage 1.503V, while the average being 1.472V.

All-core workload:


Peak voltage 1.297V, while the average being 1.259V.

VDDCR_CPU is the same reading as "CPU Core Voltage SVI2 TFN" under HWInfo, while the "command" value is what the CPU is requesting.

Since the CPU remains in control of the voltage at all times, the actual voltage will depend on the core the workload gets utilized and on the CPU specimen itself.
If you are seeing constantly over 1.5V SVI2 TFN voltages with PE4 enabled, in single threaded workloads then I suggest that you don't use PE4 on your CPU.
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