Originally Posted by guttheslayer
Where do you even get the figure from, the last I check in comparison with both GP100 and GV100, after scaling, TENSOR do not consume >5% of the die. It is in fact negligible.
Originally Posted by ILoveHighDPI
Actually Tenser Cores take up 2/5ths of each Turing Shader Module: https://www.anandtech.com/show/13282...re-deep-dive/4
You can see their oversimplified graphic of die space allocation at the bottom of this article: https://www.pcworld.com/article/3305...x-2080-ti.html
So it's not consuming exactly 50% of the space for Cuda Cores, just 40%.
Originally Posted by 8051
So 40% wasted die space instead of 50%.
No, those schematics are not drawn to scale. For one, the register file is orders of magnitude larger than the logic (L1 cache is much larger still). When it comes to logic, FP32 units are orders of magnitude larger than INT32 units. You cannot derive resource usage from the schematics (if drawn to scale, it would be very uninformative).
On the bottom of the page the blocks "overlayed" on top of the die shot are not even in the correct place.