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post #75 of (permalink) Old 02-20-2019, 02:12 AM - Thread Starter
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Quote: Originally Posted by 8051 View Post
So 40% wasted die space instead of 50%.
EDIT: Commenting on INT32 cores is really above my head, however.
After a bit of reading it does seem that INT32 is generally useful, I assume it’s part of being a GPGPU architecture, but the quantity of INT32 cores may be exaggerated in Turing to help enable the Tenser Cores, or as a vestigial component from the Workstation design.

Quote: Originally Posted by TheBlademaster01 View Post
No, those schematics are not drawn to scale. For one, the register file is orders of magnitude larger than the logic (L1 cache is much larger still). When it comes to logic, FP32 units are orders of magnitude larger than INT32 units. You cannot derive resource usage from the schematics (if drawn to scale, it would be very uninformative).

On the bottom of the page the blocks "overlayed" on top of the die shot are not even in the correct place.
Right, ultimately it’s Nvidia telling us how they’re using the silicon.
If Nvidia wanted to tell us that Ray Tracing doesn’t add a lot of cost to the overall design they thoroughly failed at it, and gave us a lot of ammunition to say otherwise along the way.

Last edited by ryan92084; 02-20-2019 at 04:54 AM.
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