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post #4136 of (permalink) Old 03-17-2019, 11:06 AM
ajc9988
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Quote: Originally Posted by 1usmus View Post
It is time to tell you about the features that will appear in Ryzen 3000


Spoiler!


Translation into simple language. We have:

1) New memory controller with partial error correction for nonECC memory
2) Desktop processor with two (2 CCD) chiplets on board, 32 threads maximum
3) New MBIST (Memory built-in self-test)
4) Core watchdog - is a fail/safe function used to reset a system in case the microprocessor gets lost due to address or data errors
5) XFR - at the moment I do not see anything special about it, the algorithm and limits have been updated. Scalar Controll come back with new processors.
6) Updated core control has a symmetric configuration of the active cores . In 2CCD configurations, each chiplet has its own RAM channel in order to minimize latency to memory access. 1 channel on 8 cores will be a bottleneck if you use the system in the default state.

This is not all information which I will gladden you in the near future
The XFR is actually quite impressive. If I read it right, they added FCLK, which we need to find out what that bus is doing. On Intel Skylake, Anand wrote the following:

The register in question is called the FCLK (or ‘f-clock’), which controls some of the cross-frequency compensation mechanisms between the ring interconnect of the CPU, the System Agent, and the PEG (PCI Express Graphics). Basically this means it is to do with data from the processor to the GPUs. So when data is handed from one end to another, this element of the processor manages the data buffers to allow that cross boundary migration in a lossless way. This is a ratio frequency setting which is tied directly to the base frequency of the processor (the BCLK, typically 100 MHz), and can be set at 4x, 8x or 10x for 400 MHz, 800 MHz or 1000 MHz respectively.
https://www.anandtech.com/show/9607/...-optimizations


They also now allow for the clock set on the Infinity Fabric (UCLK) to select the divisor, which means we are looking at IF being clocked equal to the memory frequency at dual rate instead of single rate (like 3200MHz instead of 1600MHz), potentially. That has a lot of implications on performance if I'm reading that correctly! EXCITED!!!

Edit: Anyone better with limits in calculus, here is some data points from a pro Intel review company, PCPerspective (Ryan Shrout ran it and Shrout Research and regularly attacked AMD, but the latency of going off CCX was shown by them, although their memory timings were crap and I get lower latency than they ever achieved as a combination of core clock, memory speed and timings, etc.).
https://www.pcper.com/reviews/Proces...ging-between-t

Another way would be to test Zen or Zen+ with Sisoft Sandra's test for calculating the latency to see the latency at different memory speeds, then, after that, extrapolate out the expected drop in latency for a speed double the single rate, meaning where the limit is that the curve is approaching as latency is not dropping linearly with the speed increase of the memory controller and therefor the Infinity Fabric. This can show how the bandwidth is double for the upcoming infinity fabric changes due to doubling the speed of the fabric, while the latency improvement would be estimated through this calculation. (math is the reason I dropped from engineering/physics in undergrad; the only way to pass calc II is to have taken calc II (even though calc I can handle this math problem)).

With that information, we can estimate a lot about the upcoming performance increase related to reduced latency, as well as looking at whether there were bandwidth limitations on data related to the IF. Unfortunately, we cannot fully get the picture, but a data point is a data point.

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Last edited by ajc9988; 03-17-2019 at 12:56 PM.
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