Overclock.net - An Overclocking Community - View Single Post - [WCCF] Intel 10nm Sunny Cove ’10th Gen Ice Lake’ ES CPU Single-Core Performance Leaks Out

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post #27 of (permalink) Old 06-17-2019, 10:12 AM
tyvar
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Quote: Originally Posted by white owl View Post
I'm not sure if they can. One reason they were having issues going to 10nm but TSMC didn't was because TSMC kept using a gold substrate or path-trace layer (some sort of layer) while Intel was moving to cobalt which is much harder to make a good electrical connection or bond to. Why? Intel obviously sees enough pros to outweigh the cons...one con being the hold up of months of new CPU sales all around the board and giving up the leader position for a while.

Sure Intel stuck with 14nm, why on earth would you attempt full production on 10nm and a new arch when you can still sell millions of chips to the masses without doing that? They actually had to retrofit 10nm production back to 14nm because they were making less than demand and you're always better off getting paid for something that's paid for vs something that's not. AMD will likely have Intel for a year or so while Intel is perfecting the process but once they do I imagine we'll see a 20-50% bump in performance over Coffee Lake and Intel will be back on it's 5-10% yearly tick tock scale unless AMD is always stepping over the top.

Intel couldn't attempt full production on 10nm, every reliable bit of information we have were yields were trash, with even tiny sub 60mm pieces of silicon having at least 1 defect (its why they only shipped 2 core CPUs with no GPU functionality and very low clocks at first), and clocking abysmally.

And the Cobalt story turned out to be false, because TSMC is also using cobalt https://fuse.wikichip.org/news/2408/...agon-855-dtco/

There was no demand for their 10nm stuff because it wasn't able to make parts anybody actually wanted at 10nm.

And the Tick in the old days used to be a die shrink, we are getting 1 more full node shrink left, and maybe a half node on that) spaced out in two and if we are lucky three half node shrinks. ( Intel 7nm/TSMC 5nm, Intel 5nm/TSMC 3nm and if we are very lucky a Intel 3nm/TSMC "1nm") after that silicon has hit the wall.
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