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post #35 of (permalink) Old 07-08-2019, 02:22 PM - Thread Starter
The Stilt
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Quote: Originally Posted by larrydavid View Post
Which voltage would potentially aid in stabilizing high FCLK frequency?
Matisse introduced a new voltage adjusment, called cLDO_VDDG. VDDG is the fabric voltage.
At default it is 0.950V however, some motherboards might increase above the default level even at stock settings.

cLDO means the voltage uses a drop-out (LDO = low drop-out) regulator.
Most cLDO voltages are regulated from the two main power rails of the CPU. In case of cLDO_VDDG and cLDO_VDDP, they are regulated from the VDDCR_SoC plane.
Because of this, there are couple rules. For example, if you set the VDDG to 1.100V, while your actual SoC voltage under load is 1.05V the VDDG will stay roughly at 1.01V max.
Likewise if you have VDDG set to 1.100V and start increasing the SoC voltage, your VDDG will raise as well. I don't have the exact figure, but you can assume that the minimum drop-out voltage (Vin-Vout) is around 40mV.
Meaning you ACTUAL SoC voltage has to be at least by this much higher, than the requested VDDG for it to take effect as it is requested.

Adjusting the SoC voltage alone, unlike on previous gen. parts doesn't do much if anything at all.
The default value is fixed 1.100V and AMD recommends keeping it at that level. Increasing the VDDG helps with the fabric overclocking in certain scenarios, but not always.
1800MHz FCLK should be doable at the default 0.9500V value and for pushing the limits it might be beneficial to increase it to =< 1.05V (1.100 - 1.125V SoC, depending on the load-line).
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