Originally Posted by epic1337
technically its not impossible to make the HBM into a shared LL cache to allow expandable DDR4 slots.
to begin with, most of Intel's Iris PRO uses this approach.
plus it would be advantageous to AMD too, the HBM IMC would be on the main chiplets, and the DDR4 IMC would be on the I/O die.
this way theres no latency penalty for the cached data, while the I/O IMC latency would be masked by the HBM.
If AMD were to use a normal memory controller and dimms as well as an HBM memory cache I would expect all data to still flow through the IO die so that it could manage what is in the HBM and what is being pulled from DDR4 and maintain the coherency between all the caches throughout the dies and package.