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post #8 of (permalink) Old 08-13-2019, 09:47 AM
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Quote: Originally Posted by EniGma1987 View Post
If AMD were to use a normal memory controller and dimms as well as an HBM memory cache I would expect all data to still flow through the IO die so that it could manage what is in the HBM and what is being pulled from DDR4 and maintain the coherency between all the caches throughout the dies and package.
yes and no, it would depend on how it is implemented.
if it functioned like a normal cache (e.g. the HBM is invisible to users) then it would only evict data from the cache when its full, and only access DRAM when it misses.
if it functioned like a DRAM extension (e.g. HBM+DRAM are additive), it will occasionally access the DRAM to synchronize but it could be minimized, so you'd still get the benefit of high-speed on-package cache.

edit: Intel's eDRAM is configured like the first one, and you can see how much Broadwell-C benefited from a meager 128MB cache.

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Last edited by epic1337; 08-13-2019 at 09:55 AM.
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