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post #10426 of (permalink) Old 11-07-2019, 08:14 PM
Jpmboy
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Quote: Originally Posted by Imprezzion View Post
True true. I'll be a bit more realistic. I'm going to sleep now but this looks like a pretty stable base so far. I'll let it run till morning. Will probably be at like 1500% by then. CPU is down 100Mhz and cache too so that's why core volts seem a bit high because i normally run 5.1/4.8 on this and now 5/4.7 just to be 100% sure the CPU/cache don't trigger an error lol.

These SA/IO/DRAM voltages are a bit more reasonable as well compared to the super high voltages i ran on C15 4133 which i just could not get past ~200-250% without erroring.

Now, To work on the tRDWR and tWRWR as they are pretty loose still and i wanna see if tRRD_L will pull 4 as well without erroring. Most other timings including the full RTL/IO suite have been tweaked to the point of no real further improvement to be gained. Maaaybe i can squeeze out a lower tWR / tCWL but i kinda doubt it lol. Is this tRAS = tCL+tRCD+1 good like this btw or should i go to hard tCL+tRCD=33? Or even a little looser? Never really understood all the different formula's and stories about tRAS.
Just be sure to verify performance and not only stability. You can have a stable setting that is very inefficient due to timing clashes (eg, op windows shorter than it takes to complete the ops it is open for) RRD_L(ong) is likely not =< RRD_S(hort)
Bathroom reading for the ram addict (and links "therein"): https://www.systemverilog.io/underst...ing-parameters

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Last edited by Jpmboy; 11-07-2019 at 08:19 PM.
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