[gizchina]TSMC’s 3nm Plant Will Start Production in 2020 - Page 2 - Overclock.net - An Overclocking Community

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[gizchina]TSMC’s 3nm Plant Will Start Production in 2020

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post #11 of 18 (permalink) Old 12-22-2018, 12:40 AM
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Quote: Originally Posted by Aussiejuggalo View Post
How much further can we shrink nodes on nm before we're stuck and need to look at other options?
dont worry there is pico, femto and may more options. all the way until we get to plank scale

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post #12 of 18 (permalink) Old 12-22-2018, 01:40 AM
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Quote: Originally Posted by Aussiejuggalo View Post
How much further can we shrink nodes on nm before we're stuck and need to look at other options?
I think we will stuck on the last node and keep increasing die size + use chiplets to keep up the performance upgrade.

We have mainstream CPU at die size of 300+mm2. If we stuck on the last node long enough without FAB upgrades, production cost for large die will be cheap enough.

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post #13 of 18 (permalink) Old 12-22-2018, 09:42 AM
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Quote: Originally Posted by mothergoose729 View Post
How close to 3nm would a 3nm node actually be? The node terminology is confusing. How much more dense are nodes actually getting?
There really should be a useful standard for naming nodes. I'm surprised that TSMC et al. haven't picked up the mantle and adopted the standard Intel proposed.

To Intel's credit it looks like they're still suggesting it, even when they are behind and it wouldn't benefit them:

https://newsroom.intel.com/editorial...e-naming-mess/

Spoiler!

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post #14 of 18 (permalink) Old 12-22-2018, 10:32 AM
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Quote: Originally Posted by NihilOC View Post
There really should be a useful standard for naming nodes. I'm surprised that TSMC et al. haven't picked up the mantle and adopted the standard Intel proposed.

To Intel's credit it looks like they're still suggesting it, even when they are behind and it wouldn't benefit them:

https://newsroom.intel.com/editorial...e-naming-mess/

Spoiler!
I think it's obvious that's for marketing reasons. I had to argue with my friend that Intel's struggle is going to be the same for TSMC. If TSMC didn't have it for 7 nm, it's because their 7 nm is not Intel's 7 nm.

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post #15 of 18 (permalink) Old 12-22-2018, 01:08 PM
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Quote: Originally Posted by NihilOC View Post
There really should be a useful standard for naming nodes. I'm surprised that TSMC et al. haven't picked up the mantle and adopted the standard Intel proposed.

To Intel's credit it looks like they're still suggesting it, even when they are behind and it wouldn't benefit them:

https://newsroom.intel.com/editorial...e-naming-mess/

Spoiler!



Very useful graph, and it is true that very many do not understand that while the nodes seem to share comparable names - they in-fact are very hard to compare.

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post #16 of 18 (permalink) Old 12-22-2018, 09:50 PM - Thread Starter
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Quote: Originally Posted by Clocknut View Post
I think we will stuck on the last node and keep increasing die size + use chiplets to keep up the performance upgrade.

We have mainstream CPU at die size of 300+mm2. If we stuck on the last node long enough without FAB upgrades, production cost for large die will be cheap enough.
+die stacking. Dump all the low power, less speedy transistors for basic IO and memory stuff on the bottom below the CPU core transistors. All that combined will let us keep things in usable package sizes for quite a while.

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post #17 of 18 (permalink) Old 12-22-2018, 10:23 PM
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Quote: Originally Posted by Aussiejuggalo View Post
How much further can we shrink nodes on nm before we're stuck and need to look at other options?
The industry is already looking at other options, it's just that they are not mature enough yet. 3D die stacking is only viable for ram right now, but that might be how we can squeeze out another few generations. Progress are a bunch of S curves, we're at the end of the silicon S curve, it'll probably be some new tech like photonics or quantum computing that'll be the next big leap.
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post #18 of 18 (permalink) Old 12-23-2018, 11:10 PM
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