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[Adoredtv] Ryzen 3000, Radeon 3000 Series LEAKS - It's Game On!

 
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post #961 of 1013 (permalink) Old 03-09-2019, 11:26 PM
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Usually not big on paper launches but this is a special circumstance. If AMD can get just enough copies out there to reviewers and get sold out on newegg I say go for it because they haven’t had the performance crown for at least 13 years. That would really light a fire under Intel.

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post #962 of 1013 (permalink) Old 03-10-2019, 02:56 PM
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Quote: Originally Posted by rluker5 View Post
Hopefully the rebirth of the northbridge isn't too costly in terms of performance. It may even help, idk maybe they've figured out a way to lose some performance bottleneck.
The 3 biggest issues with the classic northbridge design was bandwidth, the fact it wasn't full duplex (could only send or receive, but not both at the same time) and that all external communication had to pass through the socket-northbridge link before getting anywhere else. There was also the issue of latency.

The I/O die solves the bulk of these issues:

1. Infinity Fabric, being a significantly newer technology, is inherently faster than any of the old FSB/QPI/HT links ever could be. It's wider and clocked higher than either one of those. This helps bandwidth.
2. It's full duplex and can send and receive at the same time. This will help latency, as the CPU or northbridge doesn't have to wait for the other to finish sending before they can do their own thing. It also doubles the overall bandwidth.
3. Communications, while still having to leave the cores to get routed, don't have to leave the socket until they're sent directly to the destination PHYs. This saves power as the environment between the cores and the communications hardware is always the same, and thus can be far more tightly tuned, resulting in lower latency and higher bandwidth.

There's also the rumor currently going around that AMD has decoupled the IF/Mem clocks. If true, AMD (or the end-user) could really clock the Core-I/O links to much higher values further helping bandwidth and latency. It also helps that nowadays cores have access to much larger cache pools than what was available back in the day.

Will there be a penalty for going the non-integrated route with the I/O die? Most likely. But the bonuses for doing it this way in AMD's eyes outweigh the downsides, and so they're doing it.

Carter, can you explain that in *English*?
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post #963 of 1013 (permalink) Old 03-10-2019, 04:48 PM
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Quote: Originally Posted by Cyrious View Post
The 3 biggest issues with the classic northbridge design was bandwidth, the fact it wasn't full duplex (could only send or receive, but not both at the same time) and that all external communication had to pass through the socket-northbridge link before getting anywhere else. There was also the issue of latency.

The I/O die solves the bulk of these issues:

1. Infinity Fabric, being a significantly newer technology, is inherently faster than any of the old FSB/QPI/HT links ever could be. It's wider and clocked higher than either one of those. This helps bandwidth.
2. It's full duplex and can send and receive at the same time. This will help latency, as the CPU or northbridge doesn't have to wait for the other to finish sending before they can do their own thing. It also doubles the overall bandwidth.
3. Communications, while still having to leave the cores to get routed, don't have to leave the socket until they're sent directly to the destination PHYs. This saves power as the environment between the cores and the communications hardware is always the same, and thus can be far more tightly tuned, resulting in lower latency and higher bandwidth.

There's also the rumor currently going around that AMD has decoupled the IF/Mem clocks. If true, AMD (or the end-user) could really clock the Core-I/O links to much higher values further helping bandwidth and latency. It also helps that nowadays cores have access to much larger cache pools than what was available back in the day.

Will there be a penalty for going the non-integrated route with the I/O die? Most likely. But the bonuses for doing it this way in AMD's eyes outweigh the downsides, and so they're doing it.
I would hope the new northbridge interconnects would be better than the old ones. Ryzen needs way more communication capabilities than pre Athlon 64 cpus since it is many times faster. My concern is that it would be enough of a downgrade from what Ryzen currently has to make a new bottleneck. But I don't know this. That's something that will have the details shown when it comes out. Also on package, but off die latency isn't that much better than off package latency. At least with my edram cpus.

But we will see. I imagine it will be easier to raise core clocks with simplified cores. Maybe there will be a larger cache that makes ram latency much less relevant. It is nice that we are seeing some creativity again. I hope good things come from it.

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post #964 of 1013 (permalink) Old 03-10-2019, 05:47 PM
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Quote: Originally Posted by rluker5 View Post
I would hope the new northbridge interconnects would be better than the old ones. Ryzen needs way more communication capabilities than pre Athlon 64 cpus since it is many times faster. My concern is that it would be enough of a downgrade from what Ryzen currently has to make a new bottleneck. But I don't know this. That's something that will have the details shown when it comes out. Also on package, but off die latency isn't that much better than off package latency. At least with my edram cpus.

But we will see. I imagine it will be easier to raise core clocks with simplified cores. Maybe there will be a larger cache that makes ram latency much less relevant. It is nice that we are seeing some creativity again. I hope good things come from it.
Well I think it's already been (semi)confirmed that L3 cache has received a significant increase in amount per CCX, so that should help mask ram latency.

The bigger boost is that Threadripper and EPYC are both going to see their memory latencies get significantly flatter as all memory accesses only have to pass through the I/O die in and out, instead of having to slingshot across a bunch of different nodes back and forth, especially to nodes that dont have a direct link to the requesting node. That, and bandwidth, as any one CCX can now pull from all 8 memory channels simultaneously instead of being restricted to the local 2 or having to pull across IF. We'll see when the juicier details drop.

Carter, can you explain that in *English*?
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post #965 of 1013 (permalink) Old 03-10-2019, 06:35 PM
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Quote: Originally Posted by rluker5 View Post
Intel already has a separate I/O die, it is called the chipset. This new/old I/O die is the northbridge. They did away with that when they came out with the Athlon64 and Nehalem, respectively. Both of those architectures were huge advancements. There were ofc other big improvements, but the integration of the northbridge was one too. Hopefully the rebirth of the northbridge isn't too costly in terms of performance. It may even help, idk maybe they've figured out a way to lose some performance bottleneck. Reviews, benchmarks and comparison posts will let us know the details.

I'm glad we have such an open internet.

Edit: To me, an igpu is worth about $50. That is what I would pay extra over a non igpu i7/R7 to have one.

Minor clarification on the part in bold: Intel didn't get rid of the Northbridge with Nehalem right away and even later it will depend on the model, even the 32nm die shrink Westmere. When it came out on the X58 platform, the Northbridge was still there and hosted the 36 lane PCIe controller. What they did do was integrate the triple channel memory controller on the CPU die and this naturally also applies to the 32nm hexacores that were released later for the X58 platform. They only got rid of the Northbridge later for the mainstream P55 platform and even then not quite. The 45nm quad core Core i5's and i7's had the Northbridge fully integrated, but the 32nm Celerons, Pentiums, Core i3's and dual core Core i5's had a dual chip arrangement on the CPU package: a 32nm CPU die with the PCIe controller on board and then a separate 45nm iGPU chip that also hosted the memory controller, which resulted in increased memory latency on those models.


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post #966 of 1013 (permalink) Old 03-10-2019, 08:46 PM
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Thank you for the detailed clarification.

I'm not saying the chiplet I/O is a bad thing. Just that it might have some drawbacks like in single core games. But everything cpu is moving towards better utilization of more cumulative processing power and the chiplet thing is going along with that. There is only so long single core and memory latency dependent games can mask that a 5775c has 80% the processing power of a 7700k, 53% of an 8700k, 50% of a 2700, and 40% of a 9900k. And breaking up the cores is a great way to lower the heat density and price. There will just be some fodder for trolling is all. I don't think it will be some unilateral victory in the shot term like Adoredtv implies.

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post #967 of 1013 (permalink) Old 03-13-2019, 04:14 AM
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Looks like Ryzen 3000 ANN is closer then we thought:
A lot of MB got new bios with Ryzen 3000 support (even A320! on ASUS) and user on Reddit asked MSI and they confirmed that it's for new Ryzen + TPU DB listed the lineup:
https://www.reddit.com/r/Amd/comment...icted/eid8zd2/
https://www.techpowerup.com/cpudb/?c...ort=generation (look that only Ryzen 7/9 active!)
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post #968 of 1013 (permalink) Old 03-13-2019, 04:52 AM
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Wow a 5ghz clock out of the box is quite the accomplishment. Things are appearing more and more enticing.


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post #969 of 1013 (permalink) Old 03-13-2019, 05:48 AM
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Quote: Originally Posted by Hwgeek View Post
Looks like Ryzen 3000 ANN is closer then we thought:
A lot of MB got new bios with Ryzen 3000 support (even A320! on ASUS) and user on Reddit asked MSI and they confirmed that it's for new Ryzen + TPU DB listed the lineup:
https://www.reddit.com/r/Amd/comment...icted/eid8zd2/
https://www.techpowerup.com/cpudb/?c...ort=generation (look that only Ryzen 7/9 active!)
A 16 core/ 32 thread cpu @ 125 tdp sounds amazing. March release?! Take my $$$.

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post #970 of 1013 (permalink) Old 03-13-2019, 06:34 AM
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I thought these chips were not supposed to be here till june. This comes directly from TechRadar, plus I know that AMD CEO said this also.

AMD is hard at work on Zen 2, the architecture behind AMD Ryzen 3rd Generation. And, according to the latest internet rumors, we could see core counts rising up to 16 and clock speeds up to 5.0GHz. If any of this is true, the desktop processor landscape is going to be extremely compelling when these next-gen chips release sometime in mid 2019.

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