[Tom's Hardware] AMD EPYC Rome Benched: 64 Cores, 128 Threads Boosting to 2.2 GHz (for now) - Page 2 - Overclock.net - An Overclocking Community

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[Tom's Hardware] AMD EPYC Rome Benched: 64 Cores, 128 Threads Boosting to 2.2 GHz (for now)

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post #11 of 31 (permalink) Old 04-02-2019, 12:49 PM
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So it seems intels slow down is AMDs time to kick it up a notch without needing to rush. I mean i like efficiency and all but more ipc without these vulnerabilities would be nice.

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post #12 of 31 (permalink) Old 04-04-2019, 01:23 AM
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Quote: Originally Posted by mothergoose729 View Post
I was only looking at arithmetic. Good catch on multimedia. Odd that there would be such a huge difference in relative performance depending on the workload, considering Ryzen 3 architecture is only supposed to be a minor iteration on Ryzen 2.
If the new Ryzen real world performance is closer toward to its multimedia score, we are in for a real good time.

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post #13 of 31 (permalink) Old 04-04-2019, 02:57 AM
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Quote: Originally Posted by J7SC View Post
yummy..especially if there's a consumer (Threadripper) version at max (yeah, right ) 4 GHz; 16+3 phase mobo ready, willing and waiting, especially while the wallet is out for a Friday lunch...
http://www.electronics-lab.com/infin...-regulator-ai/

You mean something like that?
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post #14 of 31 (permalink) Old 04-04-2019, 03:52 AM
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Quote: Originally Posted by CynicalUnicorn View Post
Given how expensive SRAM is, there's probably a good reason for it, and I'm betting that the I/O hub has some shortcomings that will explain why.
The new MCM/chiplet design is worrying from a latency perspective. Having the memory controller on a different die will be a step backwards in that regard. The extra cache is probably to mask that.

Still, having the memory controllers all in the same place should make the new parts play better with Window's scheduler and mitigate some of the NUMA issues that were plaguing the quad active die Treadrippers.

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post #15 of 31 (permalink) Old 04-04-2019, 07:01 AM
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Quote: Originally Posted by Blameless View Post
The new MCM/chiplet design is worrying from a latency perspective. Having the memory controller on a different die will be a step backwards in that regard. The extra cache is probably to mask that.

Still, having the memory controllers all in the same place should make the new parts play better with Window's scheduler and mitigate some of the NUMA issues that were plaguing the quad active die Treadrippers.
It is the same latency hit as Ryzen already had, just averaged. Ryzen had to cross an IF bridge to get to any but the closest stick of RAM every time thus far, so this is not new. IF should be both faster and now decoupled from RAM speed to make up for any hit.

What I half expect with this 256MB L3 is that half of it will reside on the IO die as a mirror of what is on the CPU so that the chips no longer need 2 hops and to interrupt another core to access another die's L3. Also eventual HBM stacking on the IO die, per previous AMD slides.

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post #16 of 31 (permalink) Old 04-04-2019, 10:11 AM
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Quote: Originally Posted by KyadCK View Post
It is the same latency hit as Ryzen already had, just averaged.
Same average latency hit means one doesn't have to worry about locality, but also means that there is likely a latency penalty vs optimal scenarios on the earlier architecture where each die had it's own IMC.

Quote: Originally Posted by KyadCK View Post
IF should be both faster and now decoupled from RAM speed to make up for any hit.
Current information, from the new AGESA being released to support 3000 series chips, suggest it won't be fully decoupled, but will simply have a few dividers.

Quote: Originally Posted by KyadCK View Post
What I half expect with this 256MB L3 is that half of it will reside on the IO die as a mirror of what is on the CPU so that the chips no longer need 2 hops and to interrupt another core to access another die's L3.
How would coherency work here?

If it's a mirror of the local L3s it would sound like an inclusive L4 cache, rather than more L3 victim cache.

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post #17 of 31 (permalink) Old 04-04-2019, 10:40 AM
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Quote: Originally Posted by Blameless View Post
Same average latency hit means one doesn't have to worry about locality, but also means that there is likely a latency penalty vs optimal scenarios on the earlier architecture where each die had it's own IMC.

Is there really any better way of doing it? Either you have local controller in each die and incur larger penalty when having to go to a remote controller, or you have them all remote at equal distance and cover it as much as possible with aggressive prefetch cache. Both scenarios have disadvantages and the only way to get around all of it is to use a monolithic die where everything is local, which is what Intel has been doing and is just too costly to move forward with from this point. I think the new way of covering latency as much as possible with a massive cache is probably the best way to do it. This also wont be nearly as bad as in the past with the controllers on northbridge, it is still on package at least.

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post #18 of 31 (permalink) Old 04-04-2019, 12:29 PM
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Quote: Originally Posted by EniGma1987 View Post
Is there really any better way of doing it?
Overall, probably not, but there are some exceptions.

Quote: Originally Posted by EniGma1987 View Post
Either you have local controller in each die and incur larger penalty when having to go to a remote controller, or you have them all remote at equal distance and cover it as much as possible with aggressive prefetch cache. Both scenarios have disadvantages and the only way to get around all of it is to use a monolithic die where everything is local, which is what Intel has been doing and is just too costly to move forward with from this point. I think the new way of covering latency as much as possible with a massive cache is probably the best way to do it. This also wont be nearly as bad as in the past with the controllers on northbridge, it is still on package at least.
All true.

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post #19 of 31 (permalink) Old 04-07-2019, 02:43 AM
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What do you think? How many "Dummy Dies" will AMD use for the "Structural Integrity" for TR?
I am thinking that the base TR 16C will use 4 Dies with the fastest 4 active core in each Chiplet with working cache, thus 16C TR will have 128MB cache vs Ryzen 9 2X8core with 64MB cache.
So all TR will use minimum 4 Active Chiplets + Dummy dies for "Structural Integrity" :-).
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post #20 of 31 (permalink) Old 04-07-2019, 07:40 AM
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Quote: Originally Posted by Hwgeek View Post
What do you think? How many "Dummy Dies" will AMD use for the "Structural Integrity" for TR?
I am thinking that the base TR 16C will use 4 Dies with the fastest 4 active core in each Chiplet with working cache, thus 16C TR will have 128MB cache vs Ryzen 9 2X8core with 64MB cache.
So all TR will use minimum 4 Active Chiplets + Dummy dies for "Structural Integrity" :-).
I think they should replace the dummy dies with HBM and have another level of cache.

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