Originally Posted by CynicalUnicorn
Given how expensive SRAM is, there's probably a good reason for it, and I'm betting that the I/O hub has some shortcomings that will explain why.
The new MCM/chiplet design is worrying from a latency perspective. Having the memory controller on a different die will be a step backwards in that regard. The extra cache is probably to mask that.
Still, having the memory controllers all in the same place should make the new parts play better with Window's scheduler and mitigate some of the NUMA issues that were plaguing the quad active die Treadrippers.
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