Originally Posted by Raghar
14 nm is called how to get heat out of square that has higher thermal density than an electric heater. 7 nm is at least twice as hard to cool. Placing FIVR with its 80 percent efficiency under the same heatsink would be quite bad move. Especially CPUs with multiple layers would be restricted by thermals.
FIVR for VCCIO, or VCCSA would make some sense, but there is practically zero point in concentrating heat and power density to CPU on desktop.
CML-S (i.e. a 10C Coffee Lake) in question is a 14nm part.
The 80% efficiency for FIVR was for it's first iteration, on 22nm process.
I haven't seen any other numbers being released, but I'd suspect the efficiency on more recent implementations is at least somewhat more efficient.
Technically the efficiency could be increased by lowering the FIVR fSW and compensating it elsewhere in the silicon design.
Implementing FIVR or dLDO (AMD) will be more common in the future, as the node sizes will continue to shrink.
We are already at a point where the CPU voltages remain under 1.200V in high performance (clock) states. Since we are stuck with 12V VRM input voltage, we cannot go much below 1.200V output (i.e. 10% DC)
while maintaining a decent efficiency at high currents. FIVR / dLDOs are the future, unless we get a new ATX standard with the existing high current 12V replaced with e.g. a 8V one.