Unofficial AMD roadmaps 2019 to 2021 - Page 4 - Overclock.net - An Overclocking Community

Forum Jump: 

Unofficial AMD roadmaps 2019 to 2021

Reply
 
Thread Tools
post #31 of 33 (permalink) Old 07-19-2019, 02:30 PM
FX-5000
 
ShrimpBrime's Avatar
 
Join Date: Nov 2007
Posts: 962
Rep: 66 (Unique: 47)
Quote: Originally Posted by crakej View Post
They'll be introducing some tech soon that executes single threaded loads on multiple threads. If it detects something can run in another thread, it will automatically do it, meaning code not written for multithreading will gain some multithreading performance. This is going to make executing code much more efficient and give a decent performance boost even without touching clocks, ipc, or any other improvements.

Computing power is growing exponentially again - things are looking VERY interesting for the future. AMD has basically increased the computing power of the planet by magnitudes never seen before. Because of this, tech will improve faster an faster!
Love this post!!! It's very much true. Lots of idle threads for cloud based AI to utilize. The next 20 to 30 years is going to be interesting for mankind.

My 16 threads today is a super computer compared to 20 years ago. Never thought then I'd have such an outstanding PC. 20 years from now, I may find myself typing the exact same thing!


ShrimpBrime is offline  
Sponsored Links
Advertisement
 
post #32 of 33 (permalink) Old 07-19-2019, 07:09 PM
New to Overclock.net
 
tyvar's Avatar
 
Join Date: Aug 2017
Posts: 114
Rep: 14 (Unique: 10)
I think people are putting to much stock in 3d stacking. Heat dissipation problems with 3d stacking are even worse then that of die shrinks reducing area to shed heat.

At most you will see Interposer with a CPU and GPU on top plus maybe memory on top of that, but I'm skeptical if we will even see that in any wide spread use. I think everything will just be laid out 2.5d style on a interposer and thats the most we will see.

And SMT-4 isn't happening. It actually incurs a rather substantial area penalty, were talking 20% or so area of the chip to do it right, at least on both Sun and IBMs SMT-4 chips.
tyvar is offline  
post #33 of 33 (permalink) Old 07-20-2019, 08:55 AM
New to Overclock.net
 
ajc9988's Avatar
 
Join Date: Mar 2015
Posts: 485
Rep: 33 (Unique: 26)
Quote: Originally Posted by magnek View Post
Let me rephrase that: with the introduction of a $750 16-core part into the "mainstream" platform, AMD has effectively made the HEDT platform all but unnecessary except for those actually focused on "productivity" and "content creation", however you want to define those nebulous terms. It just feels... weird I guess? Almost as if AMD is saying "nonono please don't buy X599 unless you actually have a real need for MOAR COARZ (or just want to overcompensate), we already have a 16-core 3950X so please just focus on that please".



But still see my comment above.
I think you misunderstand what AMD has done. They haven't made their products unnecessary for HEDT, they are making Intel's products for HEDT unnecessary at all. If you want a professional HEDT product, with the upcoming pricing and core counts of AMD with extra PCIe lanes over Intel's products. Other than that, the 16-core AM4 3950X will likely make Intel's 18-core HEDT useless in many circumstances. What they are doing is bringing their approach to more cores for cheaper in the HEDT segment down to the mainstream segment, which absolutely destroyed sales. It's pretty simple. This has NOTHING to do with telling consumers don't buy the HEDT platform and everything to do with saying Intel's HEDT platform is useless, don't buy it.

Quote: Originally Posted by guttheslayer View Post
You are missing the point, having a $329 12C means AMD will push the lineup down by a stack, it means a 8C/16T will "downgrade" to a R5 and that is what we are hoping for, a $200+ 8C/16T that is clocked to 4.7G.

To have a gaming edge over current Intel offering, Zen 3 need to refine its latency between IF by another notch, and that is something i dont think we will see next year, aka refreshes.

And with regards to LISA comment, I think she might mean the next TR. Either way i think AMD will follow the footstep they have for TR1 and TR2, rather than go for double the cores this fast. We shall see.
That is bullspit. Yes, eventually 8-core will be moved to R5, but the frequency thing is exactly the problem. They don't need the frequency, they need software optimization and IPC. Even early samples of Intel's Ice Lake show under 4GHz, but still performing like their 5GHz products. Instead, IPC is needed and latency reductions, which would take another redesign of the IF to further reduce latency.

With TR core count, why wait? Intel has a 28-core $3000 CPU. AMD charges $1700 for the 32-core, meaning that they can put out the 64-core chips for $3000-3400, thereby neutering the Xeon 3175, which means there is NO PRICE POINT with the redesigned Zen 2 Threadripper where Intel chips will be recommended. Seeing the 3900X in flight, using multi-die and with only dual channel memory and not getting the hits like previously, there is a good chance the 24, 32, 48, and 64 chips will not suffer the same issues as first gen and second gen, making Intel's HEDT lineup meaningless except primarily for benchmarks and specific AVX-512 workloads (which are a very small percentage of actual workloads).

This is AMD dropping the hammer on Intel's HEDT lineup.

Quote: Originally Posted by GHADthc View Post
Yeah SMT4 is going to be a game changer, and negate the need for insane core counts (Though I am sure they will still push higher than 64 cores for Epyc no doubt).

I envision AMD bridging the market segments of Mainstream Desktop and HEDT into just one socket eventually, especially with SMT4 making it so they can have insane thread counts, there wont be a need for such physically huge sockets/CPU packages in the mainstream market, and we will probably max out somewhere around 64 cores with triple or quadruple the threads...I mean in just the latest generation jump from X470 to X570, they've increased lane count, and X570 boards can take up to 128GB of ram, socket AM5 and beyond will essentially be HEDT for all intents and purposes at the rate things are going.
That isn't how threads work. Threads do not work the same as cores, nor do they give equivalent performance. For each additional thread per core, you get diminishing returns. Four threads, at most, will give 50% more performance than a non-SMT core. So 1.5X is the most you will get from it, although it increases heat at the same time, thereby decreasing frequency to some extent. Also, they will need the insane packages moving forward. The market is expecting over 100 cores in the next couple years, while AMD's timeline to reach 128 cores is ahead of the industry predictions.

Also, no, AM5 WILL NOT be HEDT for all intents and purposes. What AMD has done with more cores is forced Intel's back against a wall for a couple years. Without the extra I/O and memory bandwidth, though, and until software optimizations better utilize multi-core counts that are scaling faster than the software, we will have future proof chips without ways to stretch their legs.

Instead, these high core count products have created a situation where mainstream users are now exploring content creation and uses they normally never considered, along with enhanced multi-tasking on computers in a significant way. This just gives users more.
Quote: Originally Posted by tyvar View Post
I don't think next year is going to be a refresh. I'm pretty sure we are going to get Zen 3 next year, and that its got quite substantive changes. For example the TAGES branch predictor was one of the Zen 3 teams babies, and they finished it up in time and it was easily to plug in and replace the old branch predictor, which is why we got it this year. This means they were already working on serious overhauls. vs Zen 1 and even what was planned originally for Zen 2.

I think the 4000 series will bring more changes in terms of IPC then the 2000 series did. Now how much IPC that actually might be I'm not sure. Also hoping for more clocks, even if its just 150mhz. They give us 150 now and then another 150 with Zen 4 in 2021, they will have negated Intel's realistic (golden chips aside) clock speed advantage.
You are correct. They are focusing on increasing IPC. Now, the reason the TAGE branch predictor was moved forward is they assumed the frequency would be much lower than it currently is, so they needed more IPC increase this gen to make up for it. Then TSMC figured out how to get the frequency up, so we had both great IPC AND frequency, thereby making Zen 2 pretty awesome.

For Zen 3, they are keeping up on the IPC front, while TSMC already has reached the same or better yields with the 4-layer EUV on 7nm+. Now, 6nm uses 5-layer EUV, while 5nm is all layer EUV. I foresee AMD going for 5nm in 2021, especially on the condition Intel may have 7nm products out late that year (which 7nm Intel density would be close to 3nm EUV density from TSMC, although Intel doesn't tell you that with high performance libraries, the densities are DRASTICALLY lower, meaning that TSMC HP and Intel HP, comparing 7nm to 10nm, are right in line with each other, meaning the uarch matters.

As to frequency, it depends on a lot of things. As you scale down on nodes, you increase heat density. So there should be no expectation of extra speed. That means that IPC increase is where the focus now is for performance, not just transistor density nor frequency.


Quote: Originally Posted by ozlay View Post
It would be nice if they could stack the IO die. Put it under/over the chiplets. Then we could have 32c/64t AM5?
They already have plans for use of an active interposer, along with a patent for TEC (peltier) in between logic and HBM. I do not think AM5 will get 32C though. That, by 2021, may be absurd ab initio.

But, I do see them using Hi-lo HBM or HBM3 stacked on the I/O chip with the TEC, thereby giving 8-16GB on chip for mainstream, with a bandwidth of over 250GBps, thereby meaning you likely don't need to buy DDR4/5 for supporting ram on the platform (although you still could and use that to feed it, or use Intel/Micron Xpoint memory for faster storage feeding the HBM).

For the discussion of Active Interposers, see response to next comment.
Quote: Originally Posted by tyvar View Post
I think people are putting to much stock in 3d stacking. Heat dissipation problems with 3d stacking are even worse then that of die shrinks reducing area to shed heat.

At most you will see Interposer with a CPU and GPU on top plus maybe memory on top of that, but I'm skeptical if we will even see that in any wide spread use. I think everything will just be laid out 2.5d style on a interposer and thats the most we will see.

And SMT-4 isn't happening. It actually incurs a rather substantial area penalty, were talking 20% or so area of the chip to do it right, at least on both Sun and IBMs SMT-4 chips.
I agree. 3d stacking is good in theory, but has not and will not be seen outside of low power silicon for a LONG while. Even AMD's patent of using a TEC in between the logic and the HBM seems more apt to be stuck on the I/O die rather than the core die, just because the core die puts out so much heat, if you try to overclock, the TEC would likely destroy the HBM in the process. Instead, if put on the I/O die, you still have IF latency, but you would easily be able to keep the I/O die cool with the HBM on top of it.

But, 2.5D on active interpose with HBM having its own stack and having the I/O die components integrated into the active interposer makes a lot more sense. By doing such, you get rid of the need for IF, replacing it with TSV and faster pathways that have lower latency. You then just stack out what you need.

So I think you are on the right track.

Meanwhile, 7nm+ theoretically gives an extra 18% size reduction or so, meaning doing SMT-4 may be possible, but I'm dubious. Software already has an issue on scaling to the core counts and thread counts of 22+. Server workloads do scale to it, but mainstream and even HEDT workloads do not yet. As such, I find the purpose and need a bit shaky, especially considering many schedulers had issues just dealing with Zen and Zen+.

Hopefully Zen 2 allows AMD to expand the software engineering division to help companies scale it out with thread count, with latency awareness built into the scheduler.

Desktop (Click to show)
Asus Maximus VIII Extreme, G.Skill 4133MHz - Running 3733MHz (MB limitation; I've had 4000, but...)@[email protected] 14-17-17-36-280 with Corsair CMXAF2 Ram fans, EVGA 980 Ti Classified (OC specs to come), [email protected]@1.42V everyday stable, Thermaltake Water 3.0 Ultimate AIO (push/pull 6xNoctua iPPC 3000), EVGA 1600 Ti PSU (for later SLI setups), Thermaltake X9 Cube, Intel 600P NVME
Laptop (Click to show)
P770ZM / Chi Mei 1080p 17.3" TN matte - OC to 100Hz / Intel Core i7 4790K - 4.5GHz 1.130V Static / Nvidia Geforce 980M 8GB (current OC limit of 330MHZ Core/410MHZ VRam/ [email protected]) / Kingston HyperX 32GB DDR3 [email protected] CR-2T custom SPD / Samsung 850 EVO 500GB M.2 / Intel Wifi Dual Band 7265ac+BT / Win 7 Pro x64 - custom by NTLite / 330W PSU/Prema BIOS
ajc9988 is offline  
Reply

Quick Reply
Message:
Options

Register Now

In order to be able to post messages on the Overclock.net - An Overclocking Community forums, you must first register.
Please enter your desired user name, your email address and other required details in the form below.
User Name:
If you do not want to register, fill this field only and the name will be used as user name for your post.
Password
Please enter a password for your user account. Note that passwords are case-sensitive.
Password:
Confirm Password:
Email Address
Please enter a valid email address for yourself.
Email Address:

Log-in



Currently Active Users Viewing This Thread: 1 (0 members and 1 guests)
 
Thread Tools
Show Printable Version Show Printable Version
Email this Page Email this Page


Forum Jump: 

Posting Rules  
You may post new threads
You may post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are Off
Pingbacks are Off
Refbacks are Off