Join Date: Mar 2014
Location: South Australia
Originally Posted by EniGma1987
Regardless how the CCXs communicate, with each other directly like in Zen1 or through IO die in Zen2, it is internal IF. Which already doubled in bandwidth and is not getting a speed boost in Zen3 according to AMD.
The difference is there is no extra IF latency involved with core to core traffic on the single CCD designs in zen 3 if they are one single CCX, and what was previously two seperate links to the IO die per CCX could probably be combined into one larger link. It wouldn't surprise me if the IO die was kept the same and just routed slightly differently.
Edit: Did some testing, my 3600X when at 4.2Ghz with tightened 3200C14 ram gets a core to core latency of 50.4ns average (11.4-73.5ns) and the same chip with only one CCX enabled (3+0 mode) has an average of 24.5ns (11.9-29ns) using sisoft sandra's multi core efficiency test.
Last edited by VeritronX; 10-18-2019 at 02:35 AM.