[WCCF] AMD Zen 3 set to deliver >8% IPC with 200 MHz better clock. - Page 6 - Overclock.net - An Overclocking Community
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[WCCF] AMD Zen 3 set to deliver >8% IPC with 200 MHz better clock.

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post #51 of 67 (permalink) Old 10-16-2019, 04:34 AM
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Quote: Originally Posted by guttheslayer View Post
The extra latency lies within chiplets as well, a multiple chiplet CPUs will have 2 layers of latency when communicating with the I/O


Improving the inter-CCX within chiplet (by merging them as 1 CCX) will reduce one layer of latency, which means it should bring performance improvement across all products of Zen 3, regardless if the CPU has 1 or 8 chiplet.


Hence to answer your question, no. The latency will remain between chiplet to chiplet but it will be still faster overall when compared to multiple chiplet Zen 2.
Cant they improve IF speed and IO speed? Intel ring bus seems to go at 4000 mhz ++ while Ryzen IO and IF is like same speed as your memory, 1800 mhz??
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post #52 of 67 (permalink) Old 10-16-2019, 06:35 AM
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When is Zen 3 out?

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post #53 of 67 (permalink) Old 10-16-2019, 07:42 AM
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Quote: Originally Posted by reqq View Post
Cant they improve IF speed and IO speed? Intel ring bus seems to go at 4000 mhz ++ while Ryzen IO and IF is like same speed as your memory, 1800 mhz??



There are two Infinity Fabrics, one "external" and one "internal". The external one is what goes to memory and other sockets and such and runs at memory speed. Internal one was already doubled in speed with Zen2, and that is used for inter-CCX communication and things like that. AMD has already said internal IF will not increase in Zen3.

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post #54 of 67 (permalink) Old 10-16-2019, 07:09 PM
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Quote: Originally Posted by EniGma1987 View Post
There are two Infinity Fabrics, one "external" and one "internal". The external one is what goes to memory and other sockets and such and runs at memory speed. Internal one was already doubled in speed with Zen2, and that is used for inter-CCX communication and things like that. AMD has already said internal IF will not increase in Zen3.
Well, no, not really, not for Ryzen 3/ Zen 2.

All four CCXs go to the IO bridge using IF. IO bridge goes to the RAM at just DDR, not IF. CCXs do not communicate with each other directly.

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post #55 of 67 (permalink) Old 10-17-2019, 07:50 AM
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Quote: Originally Posted by KyadCK View Post
Well, no, not really, not for Ryzen 3/ Zen 2.

All four CCXs go to the IO bridge using IF. IO bridge goes to the RAM at just DDR, not IF. CCXs do not communicate with each other directly.

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Regardless how the CCXs communicate, with each other directly like in Zen1 or through IO die in Zen2, it is internal IF. Which already doubled in bandwidth and is not getting a speed boost in Zen3 according to AMD.


Last edited by EniGma1987; 10-17-2019 at 07:54 AM.
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post #56 of 67 (permalink) Old 10-18-2019, 01:21 AM
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Quote: Originally Posted by EniGma1987 View Post
Regardless how the CCXs communicate, with each other directly like in Zen1 or through IO die in Zen2, it is internal IF. Which already doubled in bandwidth and is not getting a speed boost in Zen3 according to AMD.
The difference is there is no extra IF latency involved with core to core traffic on the single CCD designs in zen 3 if they are one single CCX, and what was previously two seperate links to the IO die per CCX could probably be combined into one larger link. It wouldn't surprise me if the IO die was kept the same and just routed slightly differently.

Edit: Did some testing, my 3600X when at 4.2Ghz with tightened 3200C14 ram gets a core to core latency of 50.4ns average (11.4-73.5ns) and the same chip with only one CCX enabled (3+0 mode) has an average of 24.5ns (11.9-29ns) using sisoft sandra's multi core efficiency test.


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post #57 of 67 (permalink) Old 10-18-2019, 07:24 AM
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am i the only one who noticed the L3 cache in the Milan CCX?
32+ MB L3, does this mean we'll encounter a die with more L3 per CCX? 64MB? 128MB?


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post #58 of 67 (permalink) Old 11-19-2019, 01:10 AM
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post #59 of 67 (permalink) Old 11-19-2019, 08:47 AM
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And in the end it turns out that the for server designed dies have more cache and clock 200MHz higher on boost clock while all of this makes zero difference for regular people retail products used for desktop PCs.
SMT4 is the same, makes sense for server farms, not for gaming
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post #60 of 67 (permalink) Old 11-19-2019, 07:11 PM - Thread Starter
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Quote: Originally Posted by JackCY View Post
And in the end it turns out that the for server designed dies have more cache and clock 200MHz higher on boost clock while all of this makes zero difference for regular people retail products used for desktop PCs.
SMT4 is the same, makes sense for server farms, not for gaming
They combined 4 Cores CCX to 8C CCX that itself is a big leap. There might be alot of others minor optimization which add up to pretty big gains.


All in all, the latest improvement will definitely help in games and we could possible see >10% more FPS compared with Zen 2 (with everything considered). That could possibly be just enough to edge out the 9900KS.

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