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[Various]Zen 3, 15-20% IPC Uplift, due Q4 2020

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post #41 of 51 (permalink) Old 05-21-2020, 05:19 AM
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Quote: Originally Posted by Slaughtahouse View Post
Off topic - Is there an "objective" archive that compares IPC across multiple generations of cpus from both AMD and Intel?

Every generation, besides going from Bulldozer to Ryzen, is advertising ~5% to 10% increases in performance. Given the amount of revisions, types of lakes (Sky Lake, Kaby Lake, Ice lake, Coffee Lake, Tiger lake, Rocket lake??) from Intel, I can't keep up. I'm still on Sandy Bridge-E and would like to see where I fit in.

Not to mention the manufacturing process are more confusing than ever with 10nm+++ or 7nm+ whatever we are at.

If any one has a recommendation and/or link to the most compiled list of information, please share.

Thanks in advance.

Not sure how helpful it'll be.

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post #42 of 51 (permalink) Old 05-21-2020, 11:13 AM
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Quote: Originally Posted by Ashura View Post
https://www.youtube.com/watch?v=KPWEdbfJ0oE

Not sure how helpful it'll be.
I found the video to be very good, I'm still rocking a i7-4790k and was wondering how it fared.

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post #43 of 51 (permalink) Old 05-23-2020, 07:04 AM
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Quote: Originally Posted by Ha-Nocri View Post
AMD said new socket is tied with DDR5. And it seems DDR5 will be in 2022. So next year, Ryzen 5xxx should be still AM4 and compatible with 5xx chipset.
You seem to be mistaken on a basic concept of what is going on here. AMD has been having close to a 14-16 month cadence. That means from the release of Zen to Zen 2, each generation got the release pushed back by a couple months. So Zen 3 coming in Q4 means that Zen 4 would be pushed to Q1 2022, most likely, instead of Q4 2021.

It is that basic misunderstanding that has caused you to think there will be a generational release in between, when in reality, it is mere months and a likely CES launch.

So, please, think rationally in what is happening. AMD, if anything, may do a refresh in the middle of the year, like they are about to do with the 3750X and 3850X chips this summer. But that does not mean they are missing cadence.

First Zen launched in March. Zen+ was pushed to May practically. Zen 2 was July. Zen 3 is around Sept. or Oct. So Zen 4 would easily be Dec. to Jan. of the next year, which at that point, why not steal the keynote of CES again? So Zen 4 will likely be the 5000 chips. So it likely WILL NOT be compatible. The AM4 socket is dead with the next gen of chips. Long live AM5.

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post #44 of 51 (permalink) Old 05-23-2020, 08:10 AM
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Quote: Originally Posted by Slaughtahouse View Post
With that said, I will focus on performance. At is a fairer assessment given the ranges of improvements across architectures, manufacturers etc.

Thanks all for the clarity. Reps for all

Edit: With that said, should we not use "IPC" as a metric? The name of the thread indicates "15-20%" increase in IPC but from what you're saying, IPC is hard to quantify. As different instructions have different improvement (that is my understanding).

If that is the case, is "IPC" just a marketing thing or can these various websites quantify how much IPC is improved (as an average)?
https://www.guru3d.com/articles_page..._review,7.html

4th and 5th image should be what you're looking for.
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post #45 of 51 (permalink) Old 05-23-2020, 08:45 AM
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Quote: Originally Posted by aayman_farzand View Post
https://www.guru3d.com/articles_page..._review,7.html

4th and 5th image should be what you're looking for.
To talk about that review (which the reviewer doesn't fully get it, IMO) and the question presented to you, IPC means Instruction Per Cycle. If you want actual performance, something that reviewer hinted at in mentioning the "higher frequency allowances," then you want IPS, which means Instructions Per Second.

Now IPC varies by task. That means depending on the instruction set and how coded, you will get variances. This measure can bake in multiple aspects of architecture changes, from cache changes, latency impacting the completion of the cycle, and even memory speeds effecting the feeding of cache and per core.

I previously argued with Anton over at anandtech on the topic of whether the memory speed and timings/latency need standardized for IPC, with his position being that software should be used that can separate the IPC when running the chip at stock values with stock memory configurations so that there is not artificial gimping of other elements of the architecture, like slower memory effecting keeping the cores fed or cache speed being dropped due to dropping core speed, thereby artificially changing the behavior of something other than the core but which effects the core's performance. It is a good argument. And this is why he uses SPEC for checking IPC.

IPC also varies by task and instruction set, so saying one number for IPC also becomes problematic.

Now, when you multiply IPC by the frequency (which is how many cycles that complete in a period, typically a second), you now arrive at IPS. This is more commonly seen as overall performance.

How these play together is decently straight forward. If you have an IPC of 1.2 (20% higher than another chip) and a speed of 4GHz, 1.2*4=4.8 for your IPS. If you instead have an IPC of 1, but a speed of 5GHz, 1*5=5 IPS. Welcome to the comparison of AMD Zen and Zen+ versus Intel, or even Zen 2.

So IPC bakes in certain issues, like latency effects, but it is only seen in certain tasks. If the task is latency sensitive, you could see a dive in performance. If the test is setup so it all stays within the cache system and doesn't do memory calls, then with Zen, due to the architecture, you may get a higher number.

This is why, although it is good to know and understand, there is much more to the performance of a chip. This should also show why IPC is harder to discuss, is a short hand for gains in an architecture, but is not the end, nor should it ever be, of overall performance.

But, it is NOT just a marketing thing. It is quantifiable by task, so long as you have a task with a set number of instructions, you are able to control for the frequency to be factored out (backing it from IPS to IPC), thereby allowing for a performance analysis. But trying to pinpoint how much IPC came from which change, now you are talking voodoo. That can be difficult to impossible at times, mainly because we did not design the chips nor test the effects in between each proposed change/revision.

I hope that helps (and I'm sure it causes more questions to arise)...

Edit: To be clear, setting the speed where all chips can hit it and trying to set the memory to equalize frequency and latency of the memory is trying to control factors to compare different architectures of CPU and gives an idea of behavior of the core. But, this also at times can be misleading as it can effect other aspects of the architecture that contribute to IPC, such as latency or cache behavior.

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post #46 of 51 (permalink) Old 05-23-2020, 10:36 AM
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Quote: Originally Posted by ajc9988 View Post
To talk about that review (which the reviewer doesn't fully get it, IMO) and the question presented to you, IPC means Instruction Per Cycle. If you want actual performance, something that reviewer hinted at in mentioning the "higher frequency allowances," then you want IPS, which means Instructions Per Second.

Now IPC varies by task. That means depending on the instruction set and how coded, you will get variances. This measure can bake in multiple aspects of architecture changes, from cache changes, latency impacting the completion of the cycle, and even memory speeds effecting the feeding of cache and per core.

I previously argued with Anton over at anandtech on the topic of whether the memory speed and timings/latency need standardized for IPC, with his position being that software should be used that can separate the IPC when running the chip at stock values with stock memory configurations so that there is not artificial gimping of other elements of the architecture, like slower memory effecting keeping the cores fed or cache speed being dropped due to dropping core speed, thereby artificially changing the behavior of something other than the core but which effects the core's performance. It is a good argument. And this is why he uses SPEC for checking IPC.

IPC also varies by task and instruction set, so saying one number for IPC also becomes problematic.

Now, when you multiply IPC by the frequency (which is how many cycles that complete in a period, typically a second), you now arrive at IPS. This is more commonly seen as overall performance.

How these play together is decently straight forward. If you have an IPC of 1.2 (20% higher than another chip) and a speed of 4GHz, 1.2*4=4.8 for your IPS. If you instead have an IPC of 1, but a speed of 5GHz, 1*5=5 IPS. Welcome to the comparison of AMD Zen and Zen+ versus Intel, or even Zen 2.

So IPC bakes in certain issues, like latency effects, but it is only seen in certain tasks. If the task is latency sensitive, you could see a dive in performance. If the test is setup so it all stays within the cache system and doesn't do memory calls, then with Zen, due to the architecture, you may get a higher number.

This is why, although it is good to know and understand, there is much more to the performance of a chip. This should also show why IPC is harder to discuss, is a short hand for gains in an architecture, but is not the end, nor should it ever be, of overall performance.

But, it is NOT just a marketing thing. It is quantifiable by task, so long as you have a task with a set number of instructions, you are able to control for the frequency to be factored out (backing it from IPS to IPC), thereby allowing for a performance analysis. But trying to pinpoint how much IPC came from which change, now you are talking voodoo. That can be difficult to impossible at times, mainly because we did not design the chips nor test the effects in between each proposed change/revision.

I hope that helps (and I'm sure it causes more questions to arise)...

Edit: To be clear, setting the speed where all chips can hit it and trying to set the memory to equalize frequency and latency of the memory is trying to control factors to compare different architectures of CPU and gives an idea of behavior of the core. But, this also at times can be misleading as it can effect other aspects of the architecture that contribute to IPC, such as latency or cache behavior.
Then it gets even more complicated when you factor in different SMT implementations, cache sizes, interlink speeds/designs, overall latencies, instruction sets...

People forget a "core" is not one ALU and one FPU, it's many, at different bit widths, functions, etc. IPC itself is an accumulation of the decoder performance, cache performance, memory access performance, cache hit/miss ratios and many other metrics, which can each be measured separately. Thus, IPC will change on supporting hardware, application, and even compiler version.

It is easier to quantify CPU performance with IPS in a given task than any other metric, and frankly, that is also the only thing that matters at the end of the day. All other metrics that lead to IPS are purely academic.

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post #47 of 51 (permalink) Old 05-25-2020, 07:29 AM
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Quote: Originally Posted by KyadCK View Post
Then it gets even more complicated when you factor in different SMT implementations, cache sizes, interlink speeds/designs, overall latencies, instruction sets...

People forget a "core" is not one ALU and one FPU, it's many, at different bit widths, functions, etc. IPC itself is an accumulation of the decoder performance, cache performance, memory access performance, cache hit/miss ratios and many other metrics, which can each be measured separately. Thus, IPC will change on supporting hardware, application, and even compiler version.

It is easier to quantify CPU performance with IPS in a given task than any other metric, and frankly, that is also the only thing that matters at the end of the day. All other metrics that lead to IPS are purely academic.
Exactly. It may be nice to see, but the proof is in the cake, not the batter. IPC is what it is capable of, which varies by task and hardware configuration (memory systems, etc.), but IPS shows what was done overall, and can generally be compared to competing chips. So best to focus on that (although 15% plus 200MHz being 4% means close to 20% performance increase, in theory for the academic circle j until release). What interested me more is if they did not include latency sensitive tasks when discussing IPC increases (instead focusing on server workloads that are not effected as much as say games are), then GN's analysis of the 3300 showing significant uplift in latency sensitive tasks bodes well for this fall's 6 and 8 core chips.

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post #48 of 51 (permalink) Old 05-25-2020, 07:38 AM
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if this is true then Intel is done for. They have nothing to compete, even their new stuff is a rehash of the 9 series.

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post #49 of 51 (permalink) Old 05-25-2020, 07:41 AM
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Quote: Originally Posted by philhalo66 View Post
if this is true then Intel is done for. They have nothing to compete, even their new stuff is a rehash of the 9 series.
It may not even take the next gen. Just the rehash XT versions might do it. I mean, to win in in-game benchmarks. No need for KB and mouse.

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post #50 of 51 (permalink) Old 05-25-2020, 07:44 AM
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Quote: Originally Posted by rdr09 View Post
It may not even take the next gen. Just the rehash XT versions might do it. I mean, to win in in-game benchmarks. No need for KB and mouse.
Maybe, but if AMD prices these right they will mop the floor with intels overpriced rebranded 9 series.

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