Ivy Bridge, GEN3 (PCI-E 3.0) & Chipset Info
All About Intel Ivy Bridge: source
"If there’s one thing we love about attending IDF (the Intel Developer Forum) it’s that we usually walk away knowing pretty much everything about a next-gen Intel CPU - from its architecture, through Intel's innovations to reduce its power draw, and even how to overclock the nuts off it. This is the case with Ivy Bridge, Intel’s next-gen LGA1155 CPU family, which we expect to see in March or April of 2012."Ivy Bridge Desktop Lineup Overview: source
"Ivy Bridge is a die shrink of Sandy Bridge, from 32nm to 22nm. In Intel language, this is a "Tick", although for the graphics side, this is actually a "Tock" (i.e. new architecture). Ivy Bridge will also use Tri-Gate transistors and will be socket compatible with Sandy Bridge, so you won't need a new motherboard if you have a SNB based system already—just a BIOS update.
There will be new 7-Series chipsets, though, with support for USB 3.0 for example. The first details of Ivy Bridge leaked in May, and the latest roadmaps suggest an April 2012 release. Without further ado, let's take a look at what standard voltage Ivy Bridge CPUs are planned."
22nm and 3-D transistor Explained
Chipset Comparison: source
GEN3 & PCI-E 3.0
"The new chipset family falls under the 7-series banner. We'll see Z77, Z75, H77, Q77, Q75 and B75 available at or around launch"
PCI-Express 3.0 explained: source
"Following the tradition that goes back to AGP (remember that?), the bandwidth is again doubled from 500MB/sec or 4Gb/sec on PCI-Express 2.0 to 1GB/sec or 8Gb/sec on PCI-Express 3.0. That's per lane, in each direction. This means the total bandwidth for an 16x PCI-Express graphics slots go up from 16GB/s to 32GB/s, so it should cope better with the future demands of high performance graphics cards.
To double the bandwidth the PCI-SIG hasn't just cranked up the transfer frequency by two though, instead it's lessened the encoding overheads to make faster transfers more efficient. PCI-E Express 3.0 has the same physical characteristics as PCI-E Express 2.0, so it's backward compatible with previous versions of PCI-Express, regardless of the data encoding change."More on PCI-E 3.0 (Click to show)
PCI Express 3.0: A Protocol in Transition: source
"PCI Express 3.0 is being adopted by many companies to benefit from the increase in bandwidth, but implementing PCI Express 3.0 requires the designer to understand the new protocol, DFE interaction at the PIPE interface and special situations that exists for implementing this high-speed interface. Because of the significant scope of changes that are required when developing the PCI Express 3.0 interface, it is important to carefully manage the size and complexity of the implementation to fully realize the bandwidth improvements of the PCI Express 3.0 interface."PLX chipset? source
"Integrated into each new PLX PCIe Gen3 multi-root switch device are unique performancePAK™ features, including two non-transparency (NT) ports, four direct memory access (DMA) engines, two virtual channels (VCs), and up to 12 ports for spread spectrum clock (SSC) isolation. The NT feature enables host failover and redundancy and has been widely used by tier-one OEMs since it was developed in early PCI technology. The on-chip DMA engines enable designers to increase the performance of systems by moving data among endpoints or between memory and endpoints without sacrificing CPU bandwidth. Support for two VCs enable users to prioritize traffic to support desired quality of service (QoS). The SSC clock isolation for each x4 port of the device allows designers to create large systems with each sub-system running its own SSC clock.
PLX is the only switch vendor that offered x16 ports on PCIe Gen1 and Gen2 switches, and it continues to support x16 on today’s Gen3 devices. In addition to x16 and x8 ports, these switches offer native x2 and x4 ports that enable development of large arrays of SSD based systems with fewer switches. Also included is the support for PCIe specification engineering change notices (ECNs) such as multicast, access control service (ACS), alternative routing-ID interpretation (ARI), atomic operations, and optimized buffer flush/fill (OBFF). PLX PCIe Gen3 devices are fully backwards-compatible with Gen2/Gen1 devices and recommended for all new designs. The PLX Gen3 devices can be used to create Gen3 slots using their bridging capability in a Gen2 platform."
It's all about the numbers
Intel Expects Ivy Bridge Microprocessors to Be 7% - 25% Faster Than Sandy Bridge: source
TDP - 77w in all it's glory
"According to the documents, Intel Core i7-3770 (4 cores with HyperThreading, 3.40GHz, 8MB cache) will deliver the following advantages compared its predecessor Core i7-2600 (4 cores with HyperThreading, 3.40GHz, 8MB cache):"
- +7% higher overall SYSmark 2012 score;
- +14% higher overall HDXPRT 2011 score;
- +15% higher Cinebench 11.5 score;
- +13% better ProShow Gold 4.5 result;
- +25% faster performance in Excel 2010;
- +56% faster performance in ArcSoft Media Expresso;
- +192% higher overall 3DMark Vantage score;
- +17% faster performance in 3DMark Vantage CPU benchmark;
- +199% faster performance in 3DMark Vantage GPU benchmark;
Intel Ivy Bridge to Have Revolutionary Power Consumption: source
"In addition to high-performance Core i7-series "Ivy Bridge" chips with 77W TDP, Intel will introduce Core i5 and Core i3 "Ivy Bridge" quad-core microprocessors with 65W and 45W thermal design power as well as dual-core processors with 55W and 35W thermal envelopes. Previously, Intel recommended to use notebook-oriented 35W processors for low-power performance desktops.
Reduced power consumption does not mean lower overclockability or lower Turbo Boost improvements. Thanks to configurable thermal design power feature, system makers and end-users will be able to increase or reduce TDP in order to allow chips to more significantly increase clock-speeds in Turbo Boost mode or disable automatic overclocking in order to squeeze the chips into smaller form-factors."UPDATING IN PROGRESS
Misc:Intel’s Roadmap: Ivy Bridge, Panther Point, and SSDsIntel's Ivy Bridge Architecture Exposed
More to follow