Originally Posted by JoeRambo
If primaries are sensible, then BW is governed mostly by secondaries/tertiaries (except REFI + RFC that impact effective latency by making RAM refresh less/more often for shorter/longer periods of time).
RRD_S could be 4 to align it with tFAW of 16 ( could start crashing, cause mobo is auto correcting tFAW to 24, since RRD_S is set to 6 now ).
How are WTR_L/S dialed in? They need to be on auto while lowering WRRD_sg/dg and dialed in after to resulting values.
RDRD_sg could go to 6.
And i think main culprit could be RTP, but i have zero experience with non B-Dies, so no idea what are the requirements for this DRAM.
thank you for the quick responce the WTR_L/S is on auto and i control them with the WRRD_sg/dg , i try to tweek trtp and the other timings and i see how it goes
Last edited by underclocker78; 10-08-2019 at 03:54 AM.