Originally Posted by Jpmboy
RMA? Based on bios-set voltages? Have you measured the actual voltage with a DMM? Remember, an OC on ram is an OC on the CPU too - as you discovered. It is very "normal" for XMP to require voltage tweaks for real stability.
I'm curious - how do you know the BSODs were memory related after HCi or RT? .. and not CPU IO ?
He needs to run GSAT, not Karhu. This sounds alot like the IMC/L3 cache is not stable.
If I remember your posts about Karhu, Karhu doesn't test IMC/L3 cache stability does it?
Better tests for this is Prime95 29.8 b6, 112k-112k in place FFT with AVX disabled (crashed threads or CPU Cache L0 errors, this test will test hyperthreaded IMC L3 stability quite well) or 256k-512k AVX disabled (with or without in-place, if in-place is disabled, a small part of RAM allocated, like 10%).
And errors with virtualized instruction registers (L0 cache) are related to hyperthreaded cores, which is heavily controlled by the IMC/L3 cache. Unless the BSOD is "memory_management", it could very well be related to that.
What BSOD's were showing up? If it's system service exception, IRQL_NOT_LESS_OR_EQUAL or something, that possibly isn't caused by the DRAM itself.