*Official* Intel DDR4 24/7 Memory Stability Thread - Page 1162 - Overclock.net - An Overclocking Community
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post #11611 of 11924 (permalink) Old 02-24-2020, 05:36 PM
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Quote: Originally Posted by zGunBLADEz View Post
@Jpmboy now im summoning you for real
look what i manage to do in this second evga board what you think...
im wondering if is even stable at this point just put 17/19/17 let the board do the rest just for the time been..
Edit: pulled my usb gsat and did a run
Drooped one of the timings and tweaked a few more
17/20/17/[email protected]
Tfaw 16
Trfc 320
On that test
Looks real good to me. tRCD below 20 not stable? That tRAS is likely subbed since it is shorter than CL+RCD+RTP (all three operations have to complete within the ras ticks, and if ras is too low it cycles or, more importantly the bios microcode subs in a value to correct the timing error - which is not reported to the OS.
I managed stable 4200 with a 9900X (and 64GB, no less), but alas, using the same sticks and R6EO board, this 10980XE can't manage 4000, so I run 3733 c15 (which is pretty low true latency). The issue with 4200 and 4000 with this 10980XE is RTLs. Can't get truly stable low RTLs over time with >3733, and since these are the most important "timings" 3733 actually performs better overall. My 7980XE/R6 Apex is happily humming along at 4000c16 with very tights secondaries and RTLs. It's been in compute duty for 3 weeks now, non-stop with 3 Titan Vs. Zero reason to tweak anything on that rig.
Some screen shots:
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Last edited by Jpmboy; 02-24-2020 at 05:39 PM.
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post #11612 of 11924 (permalink) Old 02-24-2020, 07:25 PM
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Here is my starting point for my new memory. G.Skill Sniper X F4-3466C18D-16GSXW

This is my first attempt. Any hints or tips on sub-timings are welcomed and appreciated.
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post #11613 of 11924 (permalink) Old 02-24-2020, 09:03 PM
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Quote: Originally Posted by bei fei View Post
Here is my starting point for my new memory. G.Skill Sniper X F4-3466C18D-16GSXW

This is my first attempt. Any hints or tips on sub-timings are welcomed and appreciated.
Not sure if you have looked at the tutorial at the start of this forum and there is also a tutorial link in my sig.
Pay to have a read of both if you haven't already and report back. Looks like there is much to do
Are those sticks B-Die?

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post #11614 of 11924 (permalink) Old 02-24-2020, 09:53 PM
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Quote: Originally Posted by Jpmboy View Post
Quote: Originally Posted by zGunBLADEz View Post
@Jpmboy now im summoning you for real
look what i manage to do in this second evga board what you think...
im wondering if is even stable at this point just put 17/19/17 let the board do the rest just for the time been..
Edit: pulled my usb gsat and did a run
Drooped one of the timings and tweaked a few more
17/20/17/[email protected]
Tfaw 16
Trfc 320
On that test
Looks real good to me. tRCD below 20 not stable? That tRAS is likely subbed since it is shorter than CL+RCD+RTP (all three operations have to complete within the ras ticks, and if ras is too low it cycles or, more importantly the bios microcode subs in a value to correct the timing error - which is not reported to the OS.
I managed stable 4200 with a 9900X (and 64GB, no less), but alas, using the same sticks and R6EO board, this 10980XE can't manage 4000, so I run 3733 c15 (which is pretty low true latency). The issue with 4200 and 4000 with this 10980XE is RTLs. Can't get truly stable low RTLs over time with >3733, and since these are the most important "timings" 3733 actually performs better overall. My 7980XE/R6 Apex is happily humming along at 4000c16 with very tights secondaries and RTLs. It's been in compute duty for 3 weeks now, non-stop with 3 Titan Vs. Zero reason to tweak anything on that rig. [IMG class=inlineimg]/forum/images/smilies/smile.gif[/IMG]
Some screen shots:
Nice tho but i see your dilemma it makes sense tho i can do 125-130gb reads as it is still limited even when i run high multi and higher mesh i guess once you are in the 50-55ns you can call it a day in x299 even if your ram/cpu/mobo cant do better.....

The problem i have with that 20 or +3 over cl at the beginning i didnt understand why i cant lower it down on par with the other 2s.. Till my board went to heaven with a permanent code FF....

When i started cleaning everything around.. I noticed one of my sticks on the gold contacts theres a few of them that are pilled off.... The gold plating felt partially off... its not burn its been like that since day 1.. i never check them when i bought them but im sure it was like that ot it felt off.... but I never cant have stable that particular timings above lets say 3700mhz is always 3 ahead of cl.. Sometimes when i start droping down rtls that particular stick dissapear out of the 4 he is a kind of a maniac by itself. So when i notice the gold contacts i did a mem run without that stick at that time on my asus x299m on tri channel and hold and behold the timing sticked on the stress test without errors..

I can rma but i don't know if gskill will return me a same set of sticks that perform the same... This 2 kits of bdie do very nice timings i bought them together.. Trfc i can drop them as low as 300trfc with 4200MHz under 1.45mV even do 1t at that speed as well.. So its a gamble for me at this point so i just deal with it like that, to me its not that important in this system.. It will drop the latency a tiny bit but if i get another kit and i cant lower trfc as low then its like the same in the end...



I can try to plate the gold back.. I have done plating in japanese swords parts before its not that hard. But the plating kit was over 100$ back in those days... dont know exactly now i supposed it's higher now..


I left it running on ramtest still running it was like 18000% when i left to work [email protected]/20/[email protected] trfc is at 320 im tightening that one and tfaw as low as 12 the rest of timings auto is putting low ones on this board i will see.


Edit: well it passed with flying colors
im going to make the tras 38 and see if i can lower that trfc more at least to 290-300 if possible after some other tweaks..

rtls are 65s/10s @ 4200 all of them i can boot at 4400 but loose 2 sticks in the process try once just to see want it to make sure first 4200 was steady
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post #11615 of 11924 (permalink) Old 02-25-2020, 05:15 AM
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Quick question guys, is there a general rule of what is an acceptable spread between tCL & tRCD/tRP?

edit: Also, are there any secondary/tertiary that can help lower tRCD/tRP?

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Last edited by wholeeo; 02-25-2020 at 05:23 AM.
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post #11616 of 11924 (permalink) Old 02-25-2020, 05:23 AM
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Quote: Originally Posted by munternet View Post
Not sure if you have looked at the tutorial at the start of this forum and there is also a tutorial link in my sig.
Pay to have a read of both if you haven't already and report back. Looks like there is much to do
Are those sticks B-Die?
They are B-Die I verified with Typhoon Burner.

I will look at your tutorial. Thanks for the information.

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post #11617 of 11924 (permalink) Old 02-25-2020, 06:51 AM
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clean a bit the stick and swap positions it with another one its doing good so far in the bigger picture lowering it will accomplish me nothing tho but here we go XD if i pass i be ok with 2 over instead of the 3 lol
also changed rtls to 63/65/63/65 instead of all of them been 65s 0 problems
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post #11618 of 11924 (permalink) Old 02-25-2020, 09:31 AM
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post #11619 of 11924 (permalink) Old 02-25-2020, 11:13 AM
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Quote: Originally Posted by wholeeo View Post
Quick question guys, is there a general rule of what is an acceptable spread between tCL & tRCD/tRP?

edit: Also, are there any secondary/tertiary that can help lower tRCD/tRP?
It really depends on the ICs on the sticks. Hynix, micron and Samsung (and others) have margins that vary by the physical size and array of the architecture. Most require a 1 or 2 spacing between CAS and the other 2, Samsung can handle it even across the three at most but the highest frequencies(like 4800, thru 4600)... always depending on the IMC and MB of course.

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post #11620 of 11924 (permalink) Old 02-25-2020, 02:18 PM
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Quote: Originally Posted by KedarWolf View Post
Yeah, Gigabyte and Asus use T-Topology on their four stick boards which will overclock better with four DIMMs than two.
I would like to get more information on this phenomenon. My previous readings seem to suggest that T-topology was meant to compete with daisy-chain, both in the 4-dimm configuration. It doesn't make sense that T-topology 4-dimm can beat 2-dimm overclocking (in the best of both implementations.)

Now, in terms of bandwidth advantage, 4-dimm seems to have an interweave feature that improves copy speeds.

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