This thread is dedicated to showing the various memory configurations of users with DDR4 on Z170/Z270 and X99 chipsets.
There is no strict criteria here, all things Z170/X99 memory overclocking welcome. However to enter the stability chart certain criteria is to be met as this is generally speaking dedicated to showing what is obtainable on both platforms at an operational level.If using ASUS within North America you can post here
:ASUS North America Z170 Support / Q&A ThreadASUS North America X99 Support / Q&A ThreadASUS North America Z270 Support / Q&A Thread
Checkout the thermal control tool especially, this will be a god send for those who really want to push things.
How to get the best performance from Broadwell-E
X99-Deluxe II build:
X99-A II build:
Rampage V Extreme Edition 10:
http://edgeup.asus.com/2017/01/03/z270-motherboard-guide/ROG DRAM Timing Control Guide
Warning: Spoiler! (Click to show)
For stability results, using the recommendations from [email protected] found below and in the overview seem the most requisite on recent platforms:
Memory Presets: This is the place to start when overclocking memory. Identify the ICs used on the memory modules and select the relevant profile. We’ve put a tremendous amount of time configuring settings to get the most from each memory type. Once the profile is selected, various parameters in the DRAM timing section will be applied for you. From there, manual tweaking is possible as required.
Maximus Tweak: Leave on auto unless experiencing instability. Mode 1 may allow more compatibility, while Mode 2 is better for performance and some memory modules. Auto defaults to Mode 2.
Memory timings will automatically be offset according to memory module SPD and memory frequency. Should you wish to make manual adjustments, the primary settings and third timings are the most important for overall memory performance. Most timings are set in DRAM clock cycles, hence a lower value results in a more aggressive setting (unless otherwise stated).
As always, performance increases from memory tuning are marginal and are generally only noticeable during synthetic benchmarks. Either way, voltage adjustments to VDIMM, VCCIO-D, Cache Voltage and to a lesser extent CPU Core Voltage & VCCIO-A may be necessary to facilitate tighter timings.
CAS: Column Address Strobe, defines the time it takes for data to be ready for burst after a read command is issued. As CAS factors in more transactions than other primary timings, it is considered to be the most important in relation to random memory read performance. (See third timing section for further info on important timings).
To calculate the actual time period denoted by the number of clock cycles set for CAS we can use the following formula:
tCAS in Nano seconds=(CAS*2000)/Memory Frequency
This same formula can be applied to all memory timings that are set in DRAM clock cycles.
DRAM RAS TO CAS Latency: Also known as tRCD. Defines the time it takes to complete a row access after an activate command is issued to a rank of memory. This timing is of secondary importance behind CAS as memory is divided into rows and columns (each row contains 1024 column addresses). Once a row has been accessed, multiple CAS requests can be sent to the row the read or write data. While a row is “open” it is referred to as an open page. Up to eight pages can be open at any one time on a rank (a rank is one side of a memory module) of memory.
DRAM RAS# PRE Time: Also known as tRP. Defines the number of DRAM clock cycles it takes to precharge a row after a page close command is issued in preparation for the next row access to the same physical bank. As multiple pages can be open on a rank before a page close command is issued the impact of tRP towards memory performance is not as prevalent as CAS or tRCD - although the impact does increase if multiple page open and close requests are sent to the same memory IC and to a lesser extent rank (there are 8 physical ICs per rank and only one page can be open per IC at a time, making up the total of 8 open pages per rank simultaneously).
DRAM RAS Active Time: Also known as tRAS. This setting defines the number of DRAM cycles that elapse before a precharge command can be issued. The minimum clock cycles tRAS should be set to is the sum of CAS+tRCD+tRTP.
DRAM Command Mode: Also known as Command Rate. Specifies the number of DRAM clock cycles that elapse between issuing commands to the DIMMs after a chip select. The impact of Command Rate on performance can vary. For example, if most of the data requested by the CPU is in the same row, the impact of Command Rate becomes negligible. If however the banks in a rank have no open pages, and multiple banks need to be opened on that rank or across ranks, the impact of Command Rate increases.
Most DRAM module densities will operate fine with a 1N Command Rate. Memory modules containing older DRAM IC types may however need a 2N Command Rate.
Latency Boundary A sets timings for the main set of Third timings, lower is faster and tighter.
Latency Boundary B sets timings for the secondary set of Third timings, lower is faster and tighter.
Manipulating Latency Boundary A and B, negates the need for setting third timings manually, unless granular control of an individual setting is required. For most users, we recommend tuning via the Latency Boundary settings. Advanced users who are tuning for Super Pi 32M may wish to set timings manually instead.
Latency Compensator when enabled tries to make opportunistic latency compensation that may increase performance or smoothen out the Memory training process. So try and compare overclocking and performance with it enabled and disabled. You can also trying enabling it when the whole system hangs at ‘55’ or ‘03’ or ‘69’ when pushing tight timings with high frequencies.
DRAM RAS to RAS Delay:Also known as tRRD (activate to activate delay). Specifies the number of DRAM clock cycles between consecutive Activate (ACT) commands to different banks of memory on the same physical rank. The minimum spacing allowed at the chipset level is 4 DRAM clocks.
DRAM Ref Cycle Time: Also known as tRFC. Specifies the number of DRAM clocks that must elapse before a command can be issued to the DIMMs after a DRAM cell refresh.
DRAM Refresh Interval: The charge stored in DRAM cells diminishes over time and must be refreshed to avoid losing data. tREFI specifies the maximum time that can elapse before all DRAM cells are refreshed. The value for tREFI is calculated according to module density. A higher number than default is more aggressive as the cells will be refreshed less frequently.
During a refresh, the memory is not available for read or write transactions. Setting the memory to refresh more often than required can impact scores negatively in memory sensitive benchmarks. It can be worth tweaking the refresh interval to a larger value for improved performance. For 24/7 use, this setting is best left at default, as real world applications do not benefit to a noticeable degree by increasing this value.
DRAM Write Recovery Time: Defines the number of clock cycles that must elapse between a memory write operation and a precharge command. Most DRAM configurations will operate with a setting of 9 clocks up to DDR3-2500. Change to 12~16 clocks if experiencing instability.
DRAM Read to Precharge Time: Also known as tRTP. Specifies the spacing between the issuing of a read command and tRP (Precharge) when a read is followed by a page close request. The minimum possible spacing is limited by DDR3 burst length which is 4 DRAM clocks.
Most 2GB memory modules will operate fine with a setting of 4~6 clocks up to speeds of DDR3-2000 (depending upon the number of DIMMs used in tandem). High performance 4GB DIMMs (DDR3-2000+) can handle a setting of 4 clocks provided you are running 8GB of memory in total and that the processor memory controller is capable.
If running 8GB DIMMs a setting below 6 clocks at speeds higher than DDR3-1600 may be unstable so increase as required.
DRAM Four Activate Window: Also known as tFAW. This timing specifies the number of DRAM clocks that must elapse before more than four Activate commands can be sent to the same rank. The minimum spacing is tRRD*4, and since we know that the minimum value of tRRD is 4 clocks, we know that the minimum internal value for tFAW at the chipset level is 16 DRAM clocks.
As the effects of tFAW spacing are only realised after four Activates to the same DIMM, the overall performance impact of tFAW is not large, however, benchmarks like Super Pi 32m can benefit by setting tFAW to the minimum possible value.
As with tRRD, setting tFAW below its lowest possible value will result in the memory controller reverting to the lowest possible value (16 DRAM clocks or tRRD * 4).
DRAM Write to Read Delay: Also known as tWTR. Sets the number of DRAM clocks to wait before issuing a read command after a write command. The minimum internal spacing is 4 clocks. As with tRTP this value may need to be increased according to memory density and memory frequency.
DRAM CKE Minimum Pulse width: This setting can be left on Auto for all overclocking. CKE defines the minimum number of clocks that must elapse before the system can transition from normal operating to low power state and vice versa.
CAS Write Latency: CWL is column access time for write commands to the DIMMs. Typically, CWL is needs to be set at or +1 over the read CAS value. High performance DIMMs can run CWL equal to or up to 3 clocks below read CAS for benchmarking (within functional limits of the DIMMs and chipset).
On modern architectures like Haswell, page access is optimized such that back to back read timings in the third timing section can have a bigger impact on performance than primary settings. Memory interleaving and addressing optimization leads to the possibility of lots back to back read and writes (page hits) rather than random access (page misses).
In layman terms, the best way to describe this is to use the analogy of a hard drive. If data is fragmented, the head needs to move back and forth over the platter reading small bits of data. Similarly on memory, this would mean that CAS, wCL, tRCD, tRP and tRAS would factor more often - opening and closing memory pages across the DIMMs to read or write parts of data.
If data is not fragmented, the head can seek an area of the disc and read the data without needed to move back and forth. On a crude level, memory interleaving works in a similar way, ensuring that data is arranged into rows across ICs so that pages don't have to be open and closed as often to access it - this saves on excessive primary timing command requirements. That's why some of the back to back read and write timings in the third timing section of UEFI have a bigger impact on performance than the primary timings which were more important on older platforms.
If the required data is in sequence, CAS can be performed to access it and subsequent requests can be spaced by tRDRD (as low as 4 clocks). A lot of these requests can be sent before a page close request is required - which relies on the primary timing set (tRAS then tRP (tRC must elapse) followed by tRCD and then CAS). That's why the third timing spacing has more impact in memory sensitive benchmarks (memory frequency and other factors aside).
tRDRD: Sets the delay between consecutive read requests to the same page. From a performance perspective, this setting is best kept at 4 clocks. Relax only if the memory is not stable or the system will not POST. Very few memory modules can handle a setting of 4 clocks at speeds above DDR3-2400 so you may need to relax accordingly, although the performance hit may negate any gains in frequency.
tRDRD_dr: Sets the delay between consecutive read requests where the subsequent read is on a different rank. A setting of 6 clocks or higher is required for most DIMMs.
tRDRD (dd): Sets the delay between consecutive read requests where the subsequent read is on a different DIMM. A setting of 6 clocks or higher is required for most DIMMs.
tWRRD: Sets the delay between a write transaction and read command. The minimum value we recommend is tWCL+tWTR.
Auto is preferred from a stability perspective, while setting as close to the minimum value as possible is best from a performance perspective. For Super Pi 32m, try tWCl+tWTR+2 as a starting point. If that is stable, then try -1 clock, if not, add+1 and repeat until stable.
tWRRD_dr: Sets the delay between a write transaction and read command where the subsequent read is on a different rank. Keeping this setting as close to 4 clocks as possible is advised, although it will need to be relaxed to 6+ clocks at high operating frequency or when using high density memory configurations.
tWRRD_dd: Sets the delay between a write transaction and read command where the subsequent read is on a different DIMM. Keeping this setting as close to 4 clocks as possible is advised, although it will need to be relaxed to 6+ clocks at high operating frequency or when using high density memory configurations.
Dec_WRD: May give a small performance increase at speeds lower than DDR3-1600 with CAS 6. Can be left on Auto for all other use.
The following timings have a minimum spacing of Read CAS. The default rules space these settings well, so adjustment should not be required unless as a last resort. Setting equal to CAS is stressful on the DIMMs and IMC. Voltages may need to be increased to run the minimum value that POSTs.
tRDWR: Sets the delay from a read to a write transaction.
tRDWR_dr: Sets the delay from a read to a write transaction where the write is on a different rank.
tRDWR_dd: Sets the delay from a read to a write transaction where the write is on a different DIMM.
MRC Fast BOOT: When enabled, bypasses memory retraining on warm resets. Disabled retrains memory to counter any drift due to thermal changes. At higher memory frequencies the retraining process can interfere with system stability, hence this setting is enabled with auto by default. Should not need changing from Auto unless the system becomes unstable.
DRAM CLK Period: Allows the application of different memory timing settings than default for the operating frequency. Each number in the scale corresponds to a DRAM divider. The lowest setting being DDR3-800. Ordinarily, the timing set applied automatically tracks the DRAM ratio selected. This setting allows us to force timing sets from different dividers to be used with the selected DRAM ratio.
A setting of 14 is recommended for high DRAM operating frequencies. For all other use, leave on Auto.
Scrambler Setting: Alternates data patterns to minimize the impact of load transients and noise on the memory bus. A setting of optimized is recommended for most configurations.
DQ, DQS and CMD Sense Amplifier: Alters the bias on signal lines to avoid mis-reads. The Sense Amplifiers work good at Auto which lets BIOS decide the best for each. Reducing usually is better. Reducing DQ Sense and CMD Sense to -1~ -6 may stabilize things further when high VDIMM is used (2.2+v for example)
DRAM Swizzling Bit 0, 1 ,2, 3:
Enable Bit 0 for best OC most times, but disabling may help uncommon DRAM setups.
Enable Bit 1 for best OC most times, but disabling may sometimes help some 4GB DRAM modules.
Disabling Bit 2 helps high frequency overclocking at the expense of performance. Enabling improves performance but may need several tries to boot when frequencies are high and timings are tight. You can retry training when the system hangs at ‘55’ or ‘03’ or ‘69’ by pressing reset here and waiting for the rig to complete a full reset.
Enabling Bit 3 usually helps overclocking and stability unless the IMC is unstable at cold temperatures (Ln2 cooling) in which case try disabling.
RAW MHz Aid: May help to improve stability when using DRAM ratios above DDR3-3100 at the expense of performance.
IC Optimizer: IC Optimizer sets background invisible tweaks for the various DRAM ICs. Note that these were fine-tuned with specific DRAM and CPUs so it may help or harm depending on the likeness of the ones on your hands. So try with Auto first, then try with the one for your ICs and compare. These will get updated over time in future BIOSes.
Google stressapp test via Linux Mint (or another compatible Linux disti) is the best memory
stress test available. Google use this stress test to evaluate memory stability of their servers
– nothing more needs to be said about how valid that makes this as a stress test tool.
To bring up system info within Mint Terminal, type: sudo dmidecode type 17
and scroll to the relevant info.For those who do not wish to install Mint to run Stressapp test:HCI Memtest can be run via DOS or Windows. http://hcidesign.com/memtest/An instance needs to be opened for each individual thread, covering a total of 90-95% of memory, giving the OS a little breathing room.
As an example i5 6600K - 8GB RAM
4 instances with 1750MB per instance.Warning: Spoiler! (Click to show)
NOTE: Version 5.0 notes state that it's 30% faster than previous versions. For testing densities beyond 16GB - it's recommended you use 5.0 Pro.
Please submit results with the following format.GSAT Results
For sake of simplicity submitted results will only record primary timing sets, but feel free to show subsequent secondary and terts within screenshot.
Linux Mint's Stressapp test needs to be run for a minimum of 1 hour by typing stressapptest -W -s 3600 in the Terminal.
To take a screenshot in Terminal type: gnome-screenshotHCI
HCI consider 1000% to be the 'golden standard' however for larger densities this can be time consuming. A minimal coverage of two laps (200%) is required to be added to the table for HCI for density over 16GB. 16GB or less requires a minimum of 4 laps (400%)
Silent Scone--i56600K @4.6/4.3---3000Mhz-C15-16-16-39-2T----1.37v---SA 1.05v---Stressapptest----1 Hour
Silent Scone--i56600K @4.6/4.3---3000Mhz-C15-16-16-39-2T----1.37v---SA 1.05v---HCI 1500%NOTE: This is not a leaderboard, as it is not a benchmark.
This threads main purpose is to both discuss information and various results and to gauge what is possible between different configurations, DIMM capabilities and CPU samples. Results are welcome all the way up the frequency spectrum. If it's obtainable, it should be posted!
Should go without staying that general system and CPU stability should be gauged via the suggested means before attempting an outright memory stability test.
I will organise the results at some point (as well as post some of my own) this weekend and update whenever I get time