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Why doesn't Intel make an updated Broadwell 5775c?

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post #21 of 25 (permalink) Old 02-13-2020, 09:03 PM
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Quote: Originally Posted by 8051 View Post
What about petitioning Intel to make an updated eDRAM CPU like the 5775c? There seem to be a lot of 5775c fans out there.
too small of a minority, retooling an entire line would cost them months of delay, amounting to hundreds of millions in expenses and losses.
where as a few hundred thousand potential buyers means they only get to earn scrap from each.

to point out, its also one of the reasons why AMD stopped making HBM consumer GPUs, the high cost and low profit margin wasn't making it feasible.

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post #22 of 25 (permalink) Old 02-14-2020, 01:56 AM
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Quote: Originally Posted by 8051 View Post
What about petitioning Intel to make an updated eDRAM CPU like the 5775c?
Dunno, maybe instead of eDRAM using eSRAM, or more L3 cache would be better. In the early days of the Pentium processors some of the mainboard's came with a slot to add cache for the processor. I seem to remember using a 512k module at one time and it being SRAM. Then again my memory is really bad so who knows . With the i7-6800k I have, smartcache technology was introduced which means L3 can be divided up between cores to give some cores more L3 than others but I don't know if there's software that actually makes use of this.

Quote: Originally Posted by rluker5 View Post
my 4980hq is capped at 4.6,4.5,4.4,4.4
It's standard to have a top ratio limit of 46x however there's a bug that enables it to be changed higher, not something the BIOS would do unless modded and XTU wouldn't want to help. The microcode patch fixes the bug.

Here you can see the 4980HQ running with 49x ratio.

Note the presence of TSX indicates that no microcode patch has been loaded. TSX was disabled by early microcode patch due to some problems with it on the Haswell platform. It's not a big deal though for operation with ambient cooling especially given that the BCLK straps work also.

BIOS usually contains a number of microcode patches for different steppings and maybe different families. On the Z97 I have there isn't a patch for the i7-4980HQ but the board will post without one, however I replaced an early Haswell stepping which was the same size as the ver 0x17 patch for the i7-4980HQ. I've never had any ES processors so no need for those early stepping patches although it might be interesting to see what differences there might be between production and ES.

So technically you might not need a processor microcode update patch to post depending what problems exist in it's unpatched state, earlier steppings are likely to be more prone to needing a patch update.

For 8 series and BDW you would likely need Management Engine firmware patching as well as probably having to modify the BIOS to handle the specific CPUID of the processor and any extra functions, if wanted.

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post #23 of 25 (permalink) Old 02-14-2020, 07:56 AM
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Quote: Originally Posted by ucode View Post
Dunno, maybe instead of eDRAM using eSRAM, or more L3 cache would be better. In the early days of the Pentium processors some of the mainboard's came with a slot to add cache for the processor. I seem to remember using a 512k module at one time and it being SRAM. Then again my memory is really bad so who knows . With the i7-6800k I have, smartcache technology was introduced which means L3 can be divided up between cores to give some cores more L3 than others but I don't know if there's software that actually makes use of this.


It's standard to have a top ratio limit of 46x however there's a bug that enables it to be changed higher, not something the BIOS would do unless modded and XTU wouldn't want to help. The microcode patch fixes the bug.

Here you can see the 4980HQ running with 49x ratio.

Note the presence of TSX indicates that no microcode patch has been loaded. TSX was disabled by early microcode patch due to some problems with it on the Haswell platform. It's not a big deal though for operation with ambient cooling especially given that the BCLK straps work also.

BIOS usually contains a number of microcode patches for different steppings and maybe different families. On the Z97 I have there isn't a patch for the i7-4980HQ but the board will post without one, however I replaced an early Haswell stepping which was the same size as the ver 0x17 patch for the i7-4980HQ. I've never had any ES processors so no need for those early stepping patches although it might be interesting to see what differences there might be between production and ES.

So technically you might not need a processor microcode update patch to post depending what problems exist in it's unpatched state, earlier steppings are likely to be more prone to needing a patch update.

For 8 series and BDW you would likely need Management Engine firmware patching as well as probably having to modify the BIOS to handle the specific CPUID of the processor and any extra functions, if wanted.
My h81 booted the 4980hq just fine without a patch as well, but I had windows 1803 and newer on that Mobo/cpu combo the whole time I've had it so it has always been patched. I'll try removing the mcupdate.dll to see if I can get unlocked. Don't think my 4980hq will be able to but 4.9 like yours though, that's pretty good.

Thanks for answering my question about the broadwell compatibility. I didn't think it would be easy or else somebody would have done it.

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post #24 of 25 (permalink) Old 02-15-2020, 05:23 PM
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Quote: Originally Posted by 8051 View Post
I really wish I had bought a 5775c system instead of my 5820k system.
The 5820K is a faster all-round part and should even be doing better in most modern games. There will certainly be some exceptions though.

Quote: Originally Posted by ucode View Post
Also some software will benefit more than others, Winrar shows this well.
Archival software in general and WinRAR in particular is phenomenally latency and cache sensitive. It's about the best case scenario test you'll see for something like this.

Quote: Originally Posted by ucode View Post
Dunno, maybe instead of eDRAM using eSRAM, or more L3 cache would be better. In the early days of the Pentium processors some of the mainboard's came with a slot to add cache for the processor. I seem to remember using a 512k module at one time and it being SRAM.
Cache is traditionally SRAM, which is faster and more power efficient (relative to a given performance level) than DRAM because it doesn't need to be refreshed. However, SRAM is also much less dense (traditionally it takes six times as many transistors to for a given capacity of SRAM), which is one of the big reasons eDRAM was used as an alternative.

Making cache's bigger has a lot of trade-offs. Die size ballons and, all other things being equal, a larger cache will need to be higher latency to achieve the same yields.

And yes, older CPUs had back-side buses for connecting external cache to the CPU. This was largely abandoned because integrated caches could be much faster.

I still have a K6-III+ setup with 2MiB of L3 cache on the motherboard (soldered in this case, but some did come on SIMMs).

Quote: Originally Posted by ucode View Post
With the i7-6800k I have, smartcache technology was introduced which means L3 can be divided up between cores to give some cores more L3 than others but I don't know if there's software that actually makes use of this.
All the cores have access to all of the L3.

Cache is also entirely transparent to most software. The CPU itself decides what to keep and what to evict, and the CPUs always check lower cache levels before moving on to higher ones, or the main memory.

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post #25 of 25 (permalink) Old 02-16-2020, 01:03 AM
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Quote: Originally Posted by rluker5 View Post
I didn't think it would be easy or else somebody would have done it.
A closer look shows some hardware modification may be necessary too due to some special standby state, setting up some pins. So yes, not easy at all.

BTW that 4.9GHz wasn't a 24/7 OC, just for demonstration. TBH though I was hoping for something better with it being a $600 CPU when launched.

Quote: Originally Posted by Blameless View Post
All the cores have access to all of the L3.
SOP but with Cache Allocation Technology that can be changed. This article is a nice example.
http://www.belvederetrading.com/blog...hing-around-me

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