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Hawaii Bios Editing ( 290 / 290X / 295X2 / 390 / 390X )

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post #141 of 4256 (permalink) Old 07-19-2015, 01:34 PM - Thread Starter
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Quote:
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Thank you gupsterg for the benches. thumb.gif
It's nice to see some comparisons with The Stilt's memory timings, even if we squeezed them a little bit out. biggrin.gif
Looking forward to your further testing! smile.gif

No worries, TBH 1100MHz 1500MHz with 1375Mhz Stilt timings is very close to Sapphire stock rom set to same clocks.
(Historic benchmark disregard voltage offset as longer testing showed need more) (Click to show)

Accounting for the extra voltage I need to give for 1100MHz / 1500MHz regardless of stock or stock plus stilt 1375 timings rom used I think the v1 rom you did (Stilt 1250 timings all straps) is the most efficient at 1080Mhz / 1410Mhz with 31mv or 38mv offset.

Just doing some other tests tonight but also hoping to test ram more. As I do [email protected] at times I thought I'd check if they had updated client and noted these utils, thinking of using the MemtestCL to see if get ram errors with v1 rom, have you used this?
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post #142 of 4256 (permalink) Old 07-19-2015, 01:39 PM
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I've never seen MemtestCL work correctly on Hawaii parts. Random errors are produced irrespective of card or clock speeds.

I don't think it's compatible with newer versions of OCL and/or Hawaii itself.

...rightful liberty is unobstructed action according to our will within limits drawn around us by the equal rights of others. I do not add 'within the limits of the law,' because law is often but the tyrant's will, and always so when it violates the right of an individual. -- Thomas Jefferson
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post #143 of 4256 (permalink) Old 07-19-2015, 03:15 PM
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I just had a deeper look at the PT1 rom, and it seems they didn't do anything but invert the primary power play table and jack up the TDP/Power/TDC limits...really simple actually.
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Originally Posted by Insan1tyOne View Post

Warning: Spoiler! (Click to show)
I had a hunch that increasing the TDC Limit would be the most risky change to make as it directly affects the amount of amperage that can be passed through the card. This could be very dangerous if someone with a reference PCB tried to mod in the TDC Limit of lets say, a 290X Lightning which has a TDC Limit of 230 while the Reference PCB only has a TDC Limit of 200 by default. I can't image what this would do to the card. ohno-smiley02.gif

TDC limit is just a limiter. If you aren't throttling, no change here will do anything.

I ran the PT1 bios (which has a 999A limit) on a reference 290 with the stock cooler for over a year with no issues, because I never tried to pull dangerous levels of current through it with insane frequency/voltage/load combinations.

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post #144 of 4256 (permalink) Old 07-19-2015, 03:29 PM - Thread Starter
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Originally Posted by Blameless View Post

I've never seen MemtestCL work correctly on Hawaii parts. Random errors are produced irrespective of card or clock speeds.

I don't think it's compatible with newer versions of OCL and/or Hawaii itself.

Cheers thumb.gif , won't waste time on it then wink.gif .

Quote:
Originally Posted by Blameless View Post

I just had a deeper look at the PT1 rom, and it seems they didn't do anything but invert the primary power play table and jack up the TDP/Power/TDC limits...really simple actually.

None of those roms ever interested me so didn't look but good to know smile.gif .
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post #145 of 4256 (permalink) Old 07-19-2015, 03:51 PM
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anyone found where VRM frequency is stored?

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post #146 of 4256 (permalink) Old 07-19-2015, 10:41 PM
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Originally Posted by gupsterg View Post

Cheers thumb.gif , won't waste time on it then wink.gif .
None of those roms ever interested me so didn't look but good to know smile.gif .

If you replace the exe from http://fah-web.stanford.edu/MemtestCL/memtestCL-1.00-windows.zip

with

https://github.com/ihaque/memtestCL/blob/master/binaries/memtestCL.exe

It appears to work fine for upto 2000mb.
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post #147 of 4256 (permalink) Old 07-20-2015, 01:46 AM
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If you replace the exe from http://fah-web.stanford.edu/MemtestCL/memtestCL-1.00-windows.zip

with

https://github.com/ihaque/memtestCL/blob/master/binaries/memtestCL.exe

It appears to work fine for upto 2000mb.

This seems to be working. Thanks for the link.

Though it's still of somewhat limited utility if we don't have a way to detect EDC/CRC errors.

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post #148 of 4256 (permalink) Old 07-21-2015, 08:00 AM
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Originally Posted by Blameless View Post

Interesting. I'll see if I can do the same thing. Main thing holding back my memory OC are black screen crashes when transitioning back to idle voltage.

Thanks.

If you are not undervolting it should be enough to set the dpm 1-6 values of the " MEM Freq. Table" to whatever your "MEM Clock 2" value is.


I was taking a closer look at the voltage table from the Hawaii Bios Reader and its basically just 3 tables.
Which makes this nonsensical values:
Code:
   993
   993
   993
  1143
  1031
  1012
  1143
  1037
  1025
  1143
  1050
  1037
  1175
  1087
  1068
  1212
  1118
  1100
  1250
  1131
  1106
  1281
  1131
  1106
To this:
Code:
Table1 Table2 Table3
   993    993    993
  1143   1031   1012
  1143   1037   1025
  1143   1050   1037
  1175   1087   1068
  1212   1118   1100
  1250   1131   1106
  1281   1131   1106

Now I just need to know what exactly they relate to.
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post #149 of 4256 (permalink) Old 07-21-2015, 08:53 AM
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I ended up taking a different approach to getting rid of issues with high memory clocks.

I tested to see what the minimum stable core voltage I needed was to make 1500MHz memory stable. I put this voltage, plus a few notches to be sure, into the voltage table for the highest DPM level. Then I set 1500MHz as the default voltage for both the highest DPM level in memory frequency table and "mem clock 1". I left all the other voltage levels and clock settings at stock.

What used to happen was I would OC the memory from 1350 to 1500 in Windows, which affect all the 1350 memory DPM levels (1-7). Since the voltage offset I applied in MSI AB only affects the highest DPM level, anything that used the 1-6 levels would black screen crash as the memory frequency was too high.

Now, anything that uses the lower DPM levels also uses the stock memory clock, and anything that calls for the top memory clock automatically forces the highest DPM level. SO, everything is stable now. GPU accelerated browsers, suspend, sleep, hybernate, VMs with 3D acceleration...I tested every combination that crashed before and they all work. Any time the core isn't getting full voltage (not including droop), it's not getting full memory clock either.

Stock:
6258cdaf_stocktable.png

Modded:
fe0e8125_modtable.png
Quote:
Originally Posted by Osbios View Post

Now I just need to know what exactly they relate to.

The voltage table has the eight DPM levels (0-7), there are three entries for each one that seem to account for different leakage values of the ASIC.

DPM 0 is the same for all leakage levels, the rest are dependent on the specific sample.

My part is a low leakage (70% ASIC) which implies higher voltage, and my readings correspond to this level in the voltage table...the first (highest) voltage of each DPM set. I changed the voltages for the other leakage levels, just to be sure.

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post #150 of 4256 (permalink) Old 07-21-2015, 05:41 PM - Thread Starter
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Quote:
Originally Posted by Blameless View Post

I ended up taking a different approach to getting rid of issues with high memory clocks......
Quote:
Originally Posted by The Stilt 
Setting fixed voltage in place of voltage pointer will disable EVV for the given DPM state.

The "voltage table" in Hawaii Bios Reader can be removed from the software, the values are just used as a reference by the display driver (they hold no functionality).
Quote:
Originally Posted by Blameless View Post

What used to happen was I would OC the memory from 1350 to 1500 in Windows, which affect all the 1350 memory DPM levels (1-7). Since the voltage offset I applied in MSI AB only affects the highest DPM level, anything that used the 1-6 levels would black screen crash as the memory frequency was too high.

Not saying your experience is not correct, only what I've noticed on mine. A voltage offset change in MSI AB applies to all DPM levels for me and this was the same for three different cards I've tested extensively. In MSI AB when I graph voltage with 0mv offset it will be 0.968v @ idle after applying an offset idle became 0.968 plus the offset.
Quote:
Originally Posted by Blameless View Post

Warning: Spoiler! (Click to show)
Modded:
fe0e8125_modtable.png

Out of the 3 you adjusted in DPM7 (Voltage table) which are you now seeing in GPU-Z / MSI AB for VDDC?
Quote:
Originally Posted by Blameless View Post

The voltage table has the eight DPM levels (0-7), there are three entries for each one that seem to account for different leakage values of the ASIC.

DPM 0 is the same for all leakage levels, the rest are dependent on the specific sample.

My part is a low leakage (70% ASIC) which implies higher voltage, and my readings correspond to this level in the voltage table...the first (highest) voltage of each DPM set. I changed the voltages for the other leakage levels, just to be sure.

This was what OneB1t had been thinking, Guru3d post . IIRC when he changed values it did not relate to a change for him, Link:- Guru3d post

I decided to do what you did ...
Warning: Spoiler! (Click to show)

Then to test if indeed what had stabilised 1500MHz RAM with Stock GPU / volts I then proceeded to revert back the changes one by one in voltage table and it was not those changes that stabilised it.

What I noted was when you change DPM7 RAM to 1500MHz even when GPU at say 300MHz and RAM for some unknown reason is hitting 1500MHz it starts using voltage of DPM7 ie whats in the six tables .

Here is a video, left window of hawaiireader is my TST0MV rom, then you see V5 on right (flashed for video). Due to the screen capture SW running your seeing the yoyo effect in graph, note GPU clock / volts / ram .
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