I ended up taking a different approach to getting rid of issues with high memory clocks.
I tested to see what the minimum stable core voltage I needed was to make 1500MHz memory stable. I put this voltage, plus a few notches to be sure, into the voltage table for the highest DPM level. Then I set 1500MHz as the default voltage for both the highest DPM level in memory frequency table and "mem clock 1". I left all the other voltage levels and clock settings at stock.
What used to happen was I would OC the memory from 1350 to 1500 in Windows, which affect all the 1350 memory DPM levels (1-7). Since the voltage offset I applied in MSI AB only affects the highest DPM level, anything that used the 1-6 levels would black screen crash as the memory frequency was too high.
Now, anything that uses the lower DPM levels also uses the stock memory clock, and anything that calls for the top memory clock automatically forces the highest DPM level. SO, everything is stable now. GPU accelerated browsers, suspend, sleep, hybernate, VMs with 3D acceleration...I tested every combination that crashed before and they all work. Any time the core isn't getting full voltage (not including droop), it's not getting full memory clock either.
Originally Posted by Osbios
Now I just need to know what exactly they relate to.
The voltage table has the eight DPM levels (0-7), there are three entries for each one that seem to account for different leakage values of the ASIC.
DPM 0 is the same for all leakage levels, the rest are dependent on the specific sample.
My part is a low leakage (70% ASIC) which implies higher voltage, and my readings correspond to this level in the voltage table...the first (highest) voltage of each DPM set. I changed the voltages for the other leakage levels, just to be sure.