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post #4731 of 5355 (permalink) Old 12-03-2017, 01:35 AM
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Hello guys,

I have ASUS ROG-STRIX-RX580-O8G-GAMING. It has samsung chip, but I have maximum 27mh/s for eth mining. I have tried different bios edits. I can not get 30 mh/s.
If you have any experience with this card. I need your help about this issue. Also, I have added the original bios of card.

asus-rog-rx580-original.rom

https://www.asus.com/Graphics-Cards/ROG-STRIX-RX580-O8G-GAMING/
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post #4732 of 5355 (permalink) Old 12-04-2017, 07:56 AM
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Quote:
Originally Posted by bardacuda View Post

That's a good question. I don't see it either in Windows 7 but I'm pretty sure that's where it's supposed to be. Figured it only worked on Win10. If you're getting 28MH though then it's already working for you...no way you would get that without the fix.

My hashrates with Elpida memory aren't really any better so I can't help you there. You will need to make or find better custom timings. If ya do let me know wink.gif

How much do those Elpidas clock for you?
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post #4733 of 5355 (permalink) Old 12-05-2017, 04:08 PM
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hello,

i've got a XFX RX 580 8GB GTR-S Black Edition OC with samsung memory,

and i'm getting only 27 mhs in ethereum right now, can you guys help me?

here is my bios (couldnt get to upload, was getting an error).

thanks
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post #4734 of 5355 (permalink) Old 12-06-2017, 04:47 AM - Thread Starter
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Someone know why i can't edit my first post anymore? I realy want to update some informations
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post #4735 of 5355 (permalink) Old 12-06-2017, 05:23 AM
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Originally Posted by zeasy View Post

hello,

i've got a XFX RX 580 8GB GTR-S Black Edition OC with samsung memory,

and i'm getting only 27 mhs in ethereum right now, can you guys help me?

here is my bios (couldnt get to upload, was getting an error).

thanks

thumb.gif

1407.2150.1250mv.zFanOff.zip 111k .zip file
Attached Files
File Type: zip 1407.2150.1250mv.zFanOff.zip (110.7 KB, 19 views)

Dell Precision T7500 : Dual Xeon X5675 @ 3.536Ghz X 24 Threads : 48 Gigabytes : Cinebench R15 : 1505 : AMD R9 390X 8GB @ 1173Mhz 1350mv 57599 Power Limit @ 1250Mhz memory error free on tight timings / since 1500mhz+ had errors galore
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post #4736 of 5355 (permalink) Old 12-06-2017, 06:19 AM
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Hi, I think that finally I have found the structure of the ATOM_ASIC_PROFILING_INFO table for polaris, the one that is calculating the voltages for the clocks.

Is like this is a covination of info from these sources:
https://patchwork.kernel.org/patch/8652631/ https://lists.freedesktop.org/archives/amd-gfx/2016-June/000093.html

An example of the the table values are (aren't always the same): Warning: Spoiler! (Click to show)
0C 01 03 06 38 C1 01 00 80 38 01 00 38 00 06 0A
6A 24 09 00 80 1A 06 00 E8 03 00 00 0C 01 18 08
20 03 00 00 B0 04 00 00 38 C1 01 00 38 C1 01 00
00 00 00 00 00 00 00 00 00 00 00 00 34 C4 01 00
43 01 00 00 00 00 00 00 00 00 00 00 C0 FF 08 0F
08 31 AC 10 00 00 00 00 00 00 01 00 00 00 00 00
00 00 00 00 4B 00 00 00 00 00 00 00 2B 00 00 00
00 00 00 00 10 00 00 00 00 00 00 00 9B 02 00 00
03 00 00 00 B8 01 00 00 76 02 00 00 2A 03 00 00
84 03 00 00 FC 03 00 00 56 04 00 00 BA 04 00 00
14 05 00 00 00 35 0C 00 00 35 0C 00 98 E0 0E 00
90 05 10 00 38 67 10 00 E0 C8 10 00 88 2A 11 00
30 8C 11 00 A7 00 00 00 A2 04 00 00 BE 01 00 00
1B 00 00 00 00 00 0C 05 FE FF B5 9C 05 00 CE FF
FF FF 00 00 00 00 F3 0D 03 00 80 60 FE FF FD F8
FF FF 0A 03 CD FF FF FF 00 00 00 00 8A 00 F1 FF
FF FF F8 11 00 01 00 01 00 01 00 00

The structure is:
Warning: Spoiler! (Click to show)
Code:
+/* for Polars10/11 AVFS parameters */
+typedef struct  _ATOM_ASIC_PROFILING_INFO_V3_6          ulong 8bytes  ushort 2bytes  uchar 1byte
+{
+  ATOM_COMMON_TABLE_HEADER         asHeader;
+ 38 C1 01 00  ULONG  ulMaxVddc; 1c138  1.150v     //Maximum voltage for all parts, in unit of 0.01mv
+ 80 38 01 00  ULONG  ulMinVddc; 13880  800mv      //Minimum voltage for all parts, in unit of 0.01mv
+ 38 00        USHORT usLkgEuseIndex;              //Efuse Lkg_FT address ( BYTE address )
+ 06           UCHAR  ucLkgEfuseBitLSB;            //Efuse Lkg_FT bit shift in 32bit DWORD
+ 0A           UCHAR  ucLkgEfuseLength;            //Efuse Lkg_FT length
+ 6A 24 09 00  ULONG  ulLkgEncodeLn_MaxDivMin;   //value of ln(Max_Lkg_Ft/Min_Lkg_Ft ) in unit of 0.00001 ( unit=100000 )
+ 80 1A 06 00  ULONG  ulLkgEncodeMax;    //Maximum Lkg_Ft measured value ( or efuse decode value ), in unit of 0.00001 ( unit=100000 )
+ E8 03 00 00  ULONG  ulLkgEncodeMin;    //-Minimum Lkg_Ft measured value ( or efuse decode value ), in unit of 0.00001 ( unit=100000 )

+ 0C 01 18 08 20 03 00 00 B0 04  EFUSE_LINEAR_FUNC_PARAM sRoFuse; //Efuse RO info: DWORD address, bit shift, length, max/min measure value. in unit of 1.
                                                                  //Linear Function: Measured = Round ( Efuse * ( Max-Min )/(2^BitSize -1 ) + Min )

   0C 01 USHORT usEfuseIndex;         268      // Efuse Index in DWORD address, for example Index 911, usEuseIndex=112
   18    UCHAR  ucEfuseBitLSB;                 // Efuse bit LSB in DWORD address, for example Index 911, usEfuseBitLSB= 911-112*8=15
   08    UCHAR  ucEfuseLength;                 // Efuse bits length,
   [B]20 03 ULONG  ulEfuseEncodeRange;   800  max 2000     // Range = Max - Min, bit31 indicate the efuse is negative number[/B]
   [B]B0 04 ULONG  ulEfuseMin;           1200         // Min [/B]

+ 38 C1 01 00 ULONG  ulEvvDefaultVddc; 1c138 1.150v  //def="EVV_DEFAULT_VDDC" descr="return default VDDC(v) when Efuse not cut" unit="100000"/>
+ 38 C1 01 00 ULONG  ulEvvNoCalcVddc; 1c138 1.150v   //def="EVV_NOCALC_VDDC" descr="return VDDC(v) when Calculation is bad" unit="100000"/>

+ 00 00 00 00 ULONG  ulSpeed_Model;      //def="EVV_SPEED_MODEL" descr="0 = Greek model, 1 = multivariate model" unit="1"/>

+ 00 00 00 00 ULONG  ulSM_A0;     //def="EVV_SM_A0" descr="Leakage coeff(Multivariant Mode)." unit="100000"/>
+ 00 00 00 00 ULONG  ulSM_A1;     //def="EVV_SM_A1" descr="Leakage/SCLK coeff(Multivariant Mode)." unit="1000000"/>
+34 C4 01 00 ULONG  ulSM_A2;     //def="EVV_SM_A2" descr="Alpha( Greek Mode ) or VDDC/SCLK coeff(Multivariant Mode)." unit="100000"/>
+ 43 01 00 00 ULONG  ulSM_A3;     //def="EVV_SM_A3" descr="Beta( Greek Mode ) or SCLK coeff(Multivariant Mode)." unit="100000"/>
+ 00 00 00 00 ULONG  ulSM_A4;     //def="EVV_SM_A4" descr="VDDC^2/SCLK coeff(Multivariant Mode)." unit="100000"/>
+ 00 00 00 00 ULONG  ulSM_A5;     //def="EVV_SM_A5" descr="VDDC^2 coeff(Multivariant Mode)." unit="100000"/>
+ C0 FF 08 0F ULONG  ulSM_A6;     //def="EVV_SM_A6" descr="Gamma( Greek Mode ) or VDDC coeff(Multivariant Mode)." unit="100000"/>
+ 08 31 AC 10 ULONG  ulSM_A7;     //def="EVV_SM_A7" descr="Epsilon( Greek Mode ) or constant(Multivariant Mode)." unit="100000"/>

+ 00 UCHAR  ucSM_A0_sign;2B       //def="EVV_SM_A0_SIGN" descr="=0 SM_A0 is postive. =1: SM_A0 is negative" unit="1"/>
+ 00 UCHAR  ucSM_A1_sign;0        //def="EVV_SM_A1_SIGN" descr="=0 SM_A1 is postive. =1: SM_A1 is negative" unit="1"/>
+ 00 UCHAR  ucSM_A2_sign;         //def="EVV_SM_A2_SIGN" descr="=0 SM_A2 is postive. =1: SM_A2 is negative" unit="1"/>
+ 00 UCHAR  ucSM_A3_sign;         //def="EVV_SM_A3_SIGN" descr="=0 SM_A3 is postive. =1: SM_A3 is negative" unit="1"/>
+ 00 UCHAR  ucSM_A4_sign;         //def="EVV_SM_A4_SIGN" descr="=0 SM_A4 is postive. =1: SM_A4 is negative" unit="1"/>
+ 00 UCHAR  ucSM_A5_sign;         //def="EVV_SM_A5_SIGN" descr="=0 SM_A5 is postive. =1: SM_A5 is negative" unit="1"/>
+ 01 UCHAR  ucSM_A6_sign;         //def="EVV_SM_A6_SIGN" descr="=0 SM_A6 is postive. =1: SM_A6 is negative" unit="1"/>  
+ 00 UCHAR  ucSM_A7_sign;         //def="EVV_SM_A7_SIGN" descr="=0 SM_A7 is postive. =1: SM_A7 is negative" unit="1"/>

+ 00 00 00 00 ULONG  ulMargin_RO_a; //def="EVV_MARGIN_RO_A" descr="A Term to represent RO equation in Ax2+Bx+C, unit=1"
+ 00 00 00 00 ULONG  ulMargin_RO_b; //def="EVV_MARGIN_RO_B" descr="B Term to represent RO equation in Ax2+Bx+C, unit=1"
+4B 00 00 00 ULONG  ulMargin_RO_c; //def="EVV_MARGIN_RO_C" descr="C Term to represent RO equation in Ax2+Bx+C, unit=1"

+ 00 00 00 00 ULONG  ulMargin_fixed;      //def="EVV_MARGIN_FIXED" descr="Fixed MHz to add to SCLK margin, unit=1" unit="1"/>
+ 2B 00 00 00 ULONG  ulMargin_Fmax_mean;  //def="EVV_MARGIN_FMAX_MEAN" descr="Percentage to add for Fmas mean margin unit=10000" unit="10000"/>
+ 00 00 00 00 ULONG  ulMargin_plat_mean;  //def="EVV_MARGIN_PLAT_MEAN" descr="Percentage to add for platform mean margin unit=10000" unit="10000"/>
+ 10 00 00 00 ULONG  ulMargin_Fmax_sigma; //def="EVV_MARGIN_FMAX_SIGMA" descr="Percentage to add for Fmax sigma margin unit=10000" unit="10000"/>
+ 00 00 00 00 ULONG  ulMargin_plat_sigma; //def="EVV_MARGIN_PLAT_SIGMA" descr="Percentage to add for platform sigma margin unit=10000" unit="10000"/>
+ 9B 02 00 00 ULONG  ulMargin_DC_sigma;   //def="EVV_MARGIN_DC_SIGMA" descr="Regulator DC tolerance margin (mV) unit=100" unit="100"/>
+ 03 00 00 00 ULONG  ulLoadLineSlop;
 
+ B8 01 00 00 ULONG  ulaTDClimitPerDPM[8];
  76 02 00 00
  2A 03 00 00
  84 03 00 00
  FC 03 00 00 
  FC 03 00 00 
  BA 04 00 00
  14 05 00 00

+ 00 35 0C 00 ULONG  ulaNoCalcVddcPerDPM[8];
  00 35 0C 00
  98 E0 0E 00
  90 05 10 00
  38 67 10 00
  E0 C8 10 00
  88 2A 11 00
  30 8C 11 00

+ A7 00 00 00 ULONG  ulAVFS_meanNsigma_Acontant0; 
+ A2 04 00 00 ULONG  ulAVFS_meanNsigma_Acontant1; 
+ BE 01 00 00 ULONG  ulAVFS_meanNsigma_Acontant2; 
+ 1B 00 USHORT usAVFS_meanNsigma_DC_tol_sigma;
+ 00 00 USHORT usAVFS_meanNsigma_Platform_mean; 
+ 00 00 USHORT usAVFS_meanNsigma_Platform_sigma;

+ 0C 05 FE FF ULONG  ulGB_VDROOP_TABLE_CKSOFF_a0; 
+ B5 9C 05 00 ULONG  ulGB_VDROOP_TABLE_CKSOFF_a1; 
+ CE FF FF FF ULONG  ulGB_VDROOP_TABLE_CKSOFF_a2; 
+ 00 00 00 00 ULONG  ulGB_VDROOP_TABLE_CKSON_a0; 
+ F3 0D 03 00 ULONG  ulGB_VDROOP_TABLE_CKSON_a1;
+ 80 60 FE FF ULONG  ulGB_VDROOP_TABLE_CKSON_a2;
 
+ FD F8 FF FF ULONG  ulAVFSGB_FUSE_TABLE_CKSOFF_m1; 
+ 0A 03 USHORT usAVFSGB_FUSE_TABLE_CKSOFF_m2; 
+  CD FF FF FF ULONG  ulAVFSGB_FUSE_TABLE_CKSOFF_b;
+ 00 00 00 00ULONG  ulAVFSGB_FUSE_TABLE_CKSON_m1; 
+ 8A 00 USHORT usAVFSGB_FUSE_TABLE_CKSON_m2; 8A
+ F1 FF FF FF ULONG  ulAVFSGB_FUSE_TABLE_CKSON_b; 

+[B]11F8 USHORT usMaxVoltage_0_25mv;           1.150v[/B]

+ 0 UCHAR  ucEnableGB_VDROOP_TABLE_CKSOFF;
+ 1 UCHAR  ucEnableGB_VDROOP_TABLE_CKSON;
+ 0 UCHAR  ucEnableGB_FUSE_TABLE_CKSOFF;
+ 1 UCHAR  ucEnableGB_FUSE_TABLE_CKSON; 
+ 100 USHORT usPSM_Age_ComFactor; 
+ 0 UCHAR  ucEnableApplyAVFS_CKS_OFF_Voltage; 0
+ 0 UCHAR  ucReserved; 
+}ATOM_ASIC_PROFILING_INFO_V3_6;
+
 
 typedef struct _ATOM_SCLK_FCW_RANGE_ENTRY_V1{

The bolted values in the table are some values I have tested to change on my r9 380 cause I don't have a polaris gpu so I can't test them and I don't know if them are working in the same way :

+ 38 C1 01 00 ulMaxVddc; 1c138 1.150v //Maximum voltage for all parts, in unit of 0.01mv
+ 80 38 01 00 ulMinVddc; 13880 800mv //Minimum voltage for all parts, in unit of 0.01mv

+ B0 04 ULONG ulEfuseMin; 1200; ulEfuseMin Is lowering in littel increases the voltages from DPM 1 to 6 in big increase is lowering DPM 1 to 7 voltages. And increasing the voltage if is lowered

+ 34 C4 01 00 ulSM_A2;
+ 43 01 00 00 ulSM_A3;
+ C0 FF 08 0F ulSM_A6;
+ 08 31 AC 10 ulSM_A7;

Are lowering DPM 1 to 7 voltages if are lowerd and incrasing them if are increased. But I have lower scores changing them.


+ 4B 00 00 00 ulMargin_RO_c;

EDITED I MADE A MISTAKE is ulMargin_Fmax_mean not ulMargin_Fmax_sigma, sorry
+ 2B 00 00 00 ulMargin_Fmax_mean;

Are lowering DPM 1 to 7 voltages if are lowerd and incrasing them if are increased.

For my r9 380 si better to change that values to change voltages than changing the voltages in powerplay tables, the only voltages that is needed to be changed into PWP is the DPM0 voltage if you change the ulMinVddc. And is better to OC with software than with bios.

EDITED:

20 03 ulEfuseEncodeRange is like a voltage offset higher values are less volage for DPM 1 to 7, and lower values more moltage. + or - 15 or 20 devimal values for the value is ~ + or - 6.25v, but I have to test more. I don't see performance lost.

Thanks for the perason who gave me a rep+ thumb.gif
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post #4737 of 5355 (permalink) Old 12-06-2017, 12:22 PM
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Quote:
Originally Posted by chris89 View Post

@jerry225 Hows it going? dd you test the bios?

Hi @chris89, thanks for asking; yeah I had to lower the memory clock to 2085 mhz, because higher values give me some errors in hwinfo and I prefer to be as close as possible to 0.

There is something I would like to ask the community please:

I want to create my custom strap for hynix 8gb, so
I have decoded 777000000000000022AA1C00B56A6D46C0551017BE8E060C006AE6000C081420EA8900AB030000001B162C31C0313F17 thanks to r_timings
Code:
####SEQ_WR_CTL_D1####
DAT_DLY = 7
DQS_DLY = 7
DQS_XTR = 0
DAT_2Y_DLY = 0
ADR_2Y_DLY = 0
CMD_2Y_DLY = 0
OEN_DLY = 7
OEN_EXT = 0
OEN_SEL = 0
ODT_DLY = 0
ODT_EXT = 0
ADR_DLY = 0
CMD_DLY = 0
####SEQ_WR_CTL_2####
DAT_DLY_H_D0 = 0
DQS_DLY_H_D0 = 0
OEN_DLY_H_D0 = 0
DAT_DLY_H_D1 = 0
DQS_DLY_H_D1 = 0
OEN_DLY_H_D1 = 0
WCDR_EN = 0
####SEQ_PMG_TIMING####
TCKSRE = 2
TCKSRX = 2
TCKE_PULSE = 10
TCKE = 10
SEQ_IDLE = 7
TCKE_PULSE_MSB = 0
SEQ_IDLE_SS = 0
####SEQ_RAS_TIMING####
TRCDW = 21
TRCDWA = 21
TRCDR = 26
TRCDRA = 26
TRRD = 6
TRC = 70
####SEQ_CAS_TIMING####
TNOPW = 0
TNOPR = 0
TR2W = 28
TCCDL = 2
TCCDS = 5
TW2R = 16
TCL = 23
####SEQ_MISC_TIMING####
TRP_WRA = 62
TRP_RDA = 29
TRP = 26
TRFC = 192
####SEQ_MISC_TIMING2####
PA2RDATA = 0
PA2WDATA = 0
TFAW = 10
TCRCRL = 3
TCRCWL = 6
T32AW = 7
TWDATATR = 0
####ARB_DRAM_TIMING####
ACTRD = 27
ACTWR = 22
RASMACTRD = 44
RASMACTWR = 49
####ARB_DRAM_TIMING2####
RAS2RAS = 192
RP = 49
WRPLUSRP = 63
BUS_TURN = 23
####MC_SEQ_MISC####
MC_SEQ_MISC1 = 0x2014080C
MC_SEQ_MISC3 = 0xAB0089EA
MC_SEQ_MISC8 = 0x00000003

I want to improve this timing strap
is there a guide/tutorial/pdf which explains what all these lines and values mean,what the possible range of values is etc etc..., please?
I've read the PDFs in its topic but I could not find an answer.

Thanks

jerry.gifjerry.gifjerry.gifjerry.gifjerry.gifjerry.gifjerry.gifjerry.gifjerry.gif
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post #4738 of 5355 (permalink) Old 12-06-2017, 01:33 PM
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Quote:
Originally Posted by jerry225 View Post

Hi @chris89, thanks for asking; yeah I had to lower the memory clock to 2085 mhz, because higher values give me some errors in hwinfo and I prefer to be as close as possible to 0.

There is something I would like to ask the community please:

I want to create my custom strap for hynix 8gb, so
I have decoded 777000000000000022AA1C00B56A6D46C0551017BE8E060C006AE6000C081420EA8900AB030000001B162C31C0313F17 thanks to r_timings
Code:
####SEQ_WR_CTL_D1####
DAT_DLY = 7
DQS_DLY = 7
DQS_XTR = 0
DAT_2Y_DLY = 0
ADR_2Y_DLY = 0
CMD_2Y_DLY = 0
OEN_DLY = 7
OEN_EXT = 0
OEN_SEL = 0
ODT_DLY = 0
ODT_EXT = 0
ADR_DLY = 0
CMD_DLY = 0
####SEQ_WR_CTL_2####
DAT_DLY_H_D0 = 0
DQS_DLY_H_D0 = 0
OEN_DLY_H_D0 = 0
DAT_DLY_H_D1 = 0
DQS_DLY_H_D1 = 0
OEN_DLY_H_D1 = 0
WCDR_EN = 0
####SEQ_PMG_TIMING####
TCKSRE = 2
TCKSRX = 2
TCKE_PULSE = 10
TCKE = 10
SEQ_IDLE = 7
TCKE_PULSE_MSB = 0
SEQ_IDLE_SS = 0
####SEQ_RAS_TIMING####
TRCDW = 21
TRCDWA = 21
TRCDR = 26
TRCDRA = 26
TRRD = 6
TRC = 70
####SEQ_CAS_TIMING####
TNOPW = 0
TNOPR = 0
TR2W = 28
TCCDL = 2
TCCDS = 5
TW2R = 16
TCL = 23
####SEQ_MISC_TIMING####
TRP_WRA = 62
TRP_RDA = 29
TRP = 26
TRFC = 192
####SEQ_MISC_TIMING2####
PA2RDATA = 0
PA2WDATA = 0
TFAW = 10
TCRCRL = 3
TCRCWL = 6
T32AW = 7
TWDATATR = 0
####ARB_DRAM_TIMING####
ACTRD = 27
ACTWR = 22
RASMACTRD = 44
RASMACTWR = 49
####ARB_DRAM_TIMING2####
RAS2RAS = 192
RP = 49
WRPLUSRP = 63
BUS_TURN = 23
####MC_SEQ_MISC####
MC_SEQ_MISC1 = 0x2014080C
MC_SEQ_MISC3 = 0xAB0089EA
MC_SEQ_MISC8 = 0x00000003

I want to improve this timing strap
is there a guide/tutorial/pdf which explains what all these lines and values mean,what the possible range of values is etc etc..., please?
I've read the PDFs in its topic but I could not find an answer.

Thanks

You first need to understand how an algorithm works - as in, what operations are done - read, write, where and how. For example, Cryptonote/Cryptonight and Ethereum are both heavy Read oriented. So, reducing the Read timings has great impact on the hashing speeds. Thats for speed. For power efficiency, you look at which timings are not heavily used and are not part of the central logic of the algoritm. For example RAS2RAS and TRFC for both Cryptonote/night. You can increase it safely by 50%, thus reducing the power draw, while not losing almost anything as speed.

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post #4739 of 5355 (permalink) Old 12-06-2017, 03:30 PM
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Hello everyone, I have a problem, when I flash some modified BIOS in my rx580 I have 3 beeps from my motherboard when I start the pc. Windows starts up correctly and the BIOS works, I do not understand what is happening ...
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post #4740 of 5355 (permalink) Old 12-06-2017, 04:31 PM
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@jerry225

1407.2188.1250.zfan.off.1250mv.zip 110k .zip file

Your factory BIOS timings are strange ... it should go 55 to 77 to 99 to BB but instead it's like 55 to 77 to 99 to 77.

Meaning the timings gets pretty loose from 1125 to 1750 but after 1750 gets extra tight again unless we edited it?

Lets compare.

STOCK Timings on your BIOS

1750 - 999000000000000022559D0031627C4990551313BC0D060C004C04017D0714204A8900A00200712419123138C02D3D17
2000 - 777000000000000022AA1C00B56A6D46C0551017BE8E060C006AE6000C081420EA8900AB030000001B162C31C0313F17
2250 - 777000000000000022AA1C00B56A6D46C0551017BE8E060C006AE6000C081420EA8900AB030000001B162C31C0313F17

Factory RX 480 timings can hold 2266mhz but like 2188mhz no problem minimal to no errrors

1750 - 777000000000000022CC1C00106A6D4DD0571016B90D060C006AE70014051420FA8900A0030000001B11333DC0303A17
2000 - 777000000000000022CC1C0031F67E57F05711183FCFB60D006C070124081420FA8900A0030000001E123A46DB354019

Sapphire RX 580 has the best timings here...

Sapphire.RX580.8192.170511.zip 110k .zip file

1000 - 777000000000000022DD1C0029B5462960550E0F2448D3060026A2005C0B1420AA8800A0000071240E0A1C206D1E2513
1125 - 999000000000000022339D006BBD572F5055100F29C9B3070048C4005D0D14204A8900A000007124100C20247B202A13
1250 - 999000000000000022339D008CC558345055110F2D4A94080048C4005D0F14204A8900A000007124120D232889222E14
1375 - 999000000000000022339D00ADCD693A7055111131CB7409004AE4006D0114204A8900A002007124140E272D97263215
1500 - 999000000000000022339D00CE516A3E80551212B40B450A004AE400750314204A8900A002007124150F2A30A4283516
1625 - 999000000000000022449D00105A7B4480551312B88C250B004C0401750514204A8900A00200712417112E34B22A3916
1750 - 999000000000000022559D0031627C4990551313BC0D060C004C04017D0714204A8900A00200712419123138C02D3D17
2000 - BBB000000000000022889D0073EE8D53A055151743CFB60D004E24010E0A14204A8900A0030071241C143840DB324418
2250 - BBB000000000000033BB9D00D6FEAF5EC05517174BD1770F005264011E0E14204A8900A00300712420173F48F7384C1A
Attached Files
File Type: zip 1407.2188.1250.zfan.off.1250mv.zip (110.4 KB, 8 views)
File Type: zip Sapphire.RX580.8192.170511.zip (110.1 KB, 34 views)

Dell Precision T7500 : Dual Xeon X5675 @ 3.536Ghz X 24 Threads : 48 Gigabytes : Cinebench R15 : 1505 : AMD R9 390X 8GB @ 1173Mhz 1350mv 57599 Power Limit @ 1250Mhz memory error free on tight timings / since 1500mhz+ had errors galore
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