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The HBM2 Timings Thread

 
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post #1 of 7 (permalink) Old 03-07-2020, 06:51 AM - Thread Starter
Mr. ÜberMix
 
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The HBM2 Timings Thread

Hi, after months passed playing with voltages and softpowertables i finally decided to work on some custom HBM2 timings, like i did with the "UberMix" back in the Polaris days. This time i'm trying to do a more "scientific" job, collecting more data and drawing graphs to see what is appening to the score and bandwidth. This time i will be focusing only on gaming, mining is already doing enough damage to the enviroment, i'm not going to help with that.

My goal is to test every single timing and find the best ones for performance, i started with tFAW and tREF, i only have some limited data, but i will update this post and add more info with time. This is something i'm doing for myself and i think is worth sharing in a simple and clear way, someone might find it useful.


I'm currently using the Unigine Superposition benchmark as the score is pretty consistent each run. 1080p medium preset for now.

My card is a Reference Vega64 repasted with MX-4 2019. [email protected] - [email protected]
i use Eliovp/amdmemorytweak to change the timings


Here is the link to two Google Docs with the infos i collected on the subject:

>>> HBM2 Timings Study

>>> Vega/HBM2 Memory Timings Description

HBM2 Memory Timings Description
Spoiler!


More Coming Soon...

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post #2 of 7 (permalink) Old 03-08-2020, 05:13 AM
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Thanky you very much for such a nice and useful explanation and insight on HBM timings !


Subbed !

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post #3 of 7 (permalink) Old 03-09-2020, 12:51 PM - Thread Starter
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i'm a bit confused, almost all timings seem to do nothing...
only tRCDRD,tRCDWR,tFAW and tREF seem to improve bandwidth and scores. Not sure if this is because of the HBM or Vega arch

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post #4 of 7 (permalink) Old 03-10-2020, 04:36 AM - Thread Starter
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i'm starting to think that the Vega arch + Cache is the reason... reading that Navi whitepaper you can see that in the Polaris arch only the CUs are using the L2 cache(page 24), on Vega CP, RB and CUs are all using the 4MB of L2(Page 25). The L2 is feeding the GPU with data fast enough i guess
Attached Files
File Type: pdf Navi_RDNA Architecture Whitepaper.pdf (1,023.7 KB, 5 views)

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post #5 of 7 (permalink) Old 03-10-2020, 06:40 AM
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@generaleramon

Try it like so: --CL 20 --RAS 33 --RCDRD 16 --RCDWR 10 --RC 44 --RP 14 --RRDS 4 --RRDL 4 --FAW 18 --WR 16 --REF 11700 --XS 270 --XSMRS 8 --CKE 8 --RFC 234 --RFCPB 160 --WTRS 4 --WTRL 9 --RREFD 8 --MRD 8 --MOD 15 --PD 8 --CKSRE 10 --CKSRX 10

Set timings first and then change your clocks, go for high clocks (more bandwith)
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post #6 of 7 (permalink) Old 03-11-2020, 02:13 AM - Thread Starter
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Quote: Originally Posted by Eliovp View Post
@generaleramon

Try it like so: --CL 20 --RAS 33 --RCDRD 16 --RCDWR 10 --RC 44 --RP 14 --RRDS 4 --RRDL 4 --FAW 18 --WR 16 --REF 11700 --XS 270 --XSMRS 8 --CKE 8 --RFC 234 --RFCPB 160 --WTRS 4 --WTRL 9 --RREFD 8 --MRD 8 --MOD 15 --PD 8 --CKSRE 10 --CKSRX 10

Set timings first and then change your clocks, go for high clocks (more bandwith)
it's just tREF and tRFC that differ from the stock 1000Mhz strap, isn't it? the rest seem stock to me

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post #7 of 7 (permalink) Old 03-11-2020, 03:48 AM
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Quote: Originally Posted by generaleramon View Post
it's just tREF and tRFC that differ from the stock 1000Mhz strap, isn't it? the rest seem stock to me
Just an example
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