Trying to answer some questions that haven't been answered:
Originally Posted by digitalrelic
Is the 7820X also being hindered by these motherboard issues? Or is it only 10+ core CPUs?
The motherboard problem isn't much of an issue if there's any airflow nearby. Just make sure you grab a board with 8 pin+ 4 pin power connectors for the CPU.
Originally Posted by Artah
Whatever you do please don't rush/halfass the delidding and Binning, I plan to buy a 7900x and 7980xe (if the clocks are good) CPU with CLU from you, would hate to get one that didn't get the normal SL TLC. I know you have a Sunday launch but would rather have a next Sunday launch to get a carefully prepared CPU. I have not liquid cooled motherboard VRMs before but this rounds looks to call for it.
TLC is our bread and butter- we won't ship unless we're confident.
Originally Posted by zornyan
thanks for the response mate, mind if I ask what kind of delivery times you have to the UK? basically if I order Sunday what day should I roughly expect delivery?
Originally Posted by SsXxX
so if less core is less problem then more is more trouble, u can only imagine how well will the 18core ones do with the current boards, so much for a platform that is supposed to be scalable and easily upgradable
in any case i will be waiting for the rampage 6 extreme or apex and i guess those will he fine and my cpu of choice will be either the octa or the 10 core
I would wait for some of the newer boards coming out in the next few months if you're really wanting push a 7980XE hard. The R6E and Apex are both very promising boards.
Originally Posted by Mysticial
If I had to guess, the thermals on Skylake X are a hella lot more complicated than I had imagined - especially once you factor in the AVX512 and multiple ways that the CPU can throttle for various reasons.
One of my 7900X's "preferred cores" is actually not stable at stock settings (4.5 GHz) under a single-threaded AVX512 test. And the BIOS is apparently not applying any AVX or AVX512 offset by default. I'm tempted to point the finger at the motherboard/BIOS rather than the CPU itself.
The thermals are part of the issue that was holding us up. Some 7900Xs throttle at 1.05V before delidding under a full AVX512 load (just look at the latest Intel linpack). Without being able to set different voltages along with the AVX/AVX512 offsets, it's hard to push the non-AVX frequency on these chips without hitting a voltage that will cause AVX-512 to throttle. As I mentioned in our emails, I've had frequency/power throttling issues with Gigabyte boards with or without AVX. I think it's just an early bios thing.
Originally Posted by coolhandluke41
wouldn't it be easier to lower the voltage say 1.15v or even less + AVX and go for the highest clock ?..I think you need to use same voltage in order to bin properly if not then go all out for highest freq. with same cooling solution ..just my 2c
Edit; Thanks for the info and your work
As above, the lower the voltage we use to test with, the lower we will be able to advertise non-AVX clocks. It gets pretty extreme, so we have to find a balance between the two.
Originally Posted by WeirdBob
That's hotter than I expected after deliding.
Keep up the good work and thanks for the info!
These are not low temperature CPUs. Kaby lake(14nm+) was a fireball itself compared to Skylake(14nm), and these are multiple 14nm+ cores all crammed up next to each other.
Originally Posted by cerealkeller
Would you be willing to share the price you're asking for your highest binned 7900x?
Pricing will be available tomorrow at launch.
Originally Posted by Blameless
Since every part has it's own average leakage, which is where the default VID, as well as the range likely to be usable, come from, perhaps it would be best to do all the binning around a certain level of clock speed vs. cooling, rather than vs. voltage?
Sticking to one single voltage makes the high leakage parts look artificially good. They do tend to go furthest on the least voltage, but they are often so hard to cool that the practical clock limits can be lower.
This is a problem we were faced with. Things get really messy the more variables we have, and we were trying to reduce variables starting with this launch to make things simpler. We have settled with a compromise between testing with a high and low voltage, to where the low leakage parts almost meet the high leakage parts in the middle.