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Thread: NEW!!! DRAM Calculator for Ryzen™ 1.7.3 (overclocking DRAM on AM4) + MEMbench 0.8 (DRAM bench) Reply to Thread
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  Topic Review (Newest First)
07-10-2020 10:05 AM
Maghook @Veii

I've to apologize, cause:
1) Complete system purchased from a professional PC assembler who pulls some extra money for that (silent pc).
2) At first glance, I didn't like the idea of ripping out the 4 RAM sticks, since half of them were buried under the big Dark Rock 4 Pro cooler.

But then I took a look insight today and I'm happy that I did:

According to your advice the B-Dies should be in slave (A1+B1) und the therefore the E-Dies in master ch. (A2 + B2).
Now the prof. assembler obviously didn't care about the stickers of the sticks at all, as otherwise he would have noticed that different pairwise production dates und printed on version numbering of these two different kits. Of course he just pushed the sticks into the slots and didn't care for anything else.
The result: on master ch. as well as on slave one he mixed one B-Die with one E-Die. Yay...

So I changed that according to your recommendation und put everything back in.
Also I've to apologize for the bad photos I took, but seems you will have to live with that
Anyway...here they are.

Thanks!
-------
Edit:

So concerning to Short guide, baseline edition I see:
- tRAS (36) = tRCD+tCL (=>matched) or tWR+tCL+tBL (=> 34; no match would have to lower tWR=18 but does not quite seem to be a good decision)
- tRC = tRP + tRAS / +2 or +4 for stability (well, that claims for 56 which I had errors last time. 54 would be really nice with tRFC=540; is there a special rule for tRFC / tRC = even or uneven value allowed or better?)
- tWTRL = tRRDS*2 (=> uff. IIRC you once stated in another post: tWTRL = tRRDS*3. Cause of that I lowered that one from tWRTL=10 to 12)
- tWR (16) = tRAS-tRCD (optimal, check; lowest tRRDS + tWTRS ( 4 + 4 = 8, no chance ; Veii Rec. = tRTP *2 => would be 20 in my case, that one would be nice for tRFC and also tRTP but at the end: does set value to 16 or 20 make such a difference at the end?)
- SCL's (=> guess will never be tighter than 4 with my two opposite kits)
- tCWL = keep it identical to tCL (=> why? I noticed that this one alone with 14 and not 16 will do ~2ns in latency IIRC)
- tRTP = optimally clean divider of tRFC (54 =>check)
- tWRRD (=> well if I understood you correctly, than if tRDWR=10 in my case, RCD= 19(20 with GDM=on) than tWRRD doesn't have to be 4 - it could also be 1. Would GDM=on make implicitly a 2 out of this 1?)

Okay. Still have to work on voltages and CADs, procODT, RTTs.
07-10-2020 09:39 AM
pipes Why zentimings no work on my x570 system?

Inviato dal mio MI 9 utilizzando Tapatalk
07-10-2020 08:56 AM
Tobiman
Quote: Originally Posted by DeusM View Post
H guys, i have a small dilemma!


I have managed to boot at 3733cl14 and i dont think its stable because im unsure if i will damage the ram as my voltage is 1.5v


DDR4V: 1.5v
SOC:1.1v
Vddg: .950
VDDP:.900




Is this voltage safe or should i just give up on 3733cl14?
If you can keep your dram below 45 degrees celsius or lower while running TM5 then you are less likely to get errors. I used to get errors then I added extra cooling and pass all my tests. Here are my settings with dram - 1.5v, soc - 1.15, vddg & vddp - 1.050
07-10-2020 08:44 AM
LuckyBahstard
Quote: Originally Posted by Rawson View Post
copied from asus owners club

Hi. I've got 2x kits of trident z. ones a samsung b and ones a hynix a. both kits are 16-18-18-18-38-58. The hynix will do 14-17-17-17-30-32, but the Samsung won't really do anything, no 16-16-16-16 either. Will I have to do step by step tuning on the Samsung? Is this motherboards overclocking support for RAM bad or is it bottom barley B die? I didn't expect B die to perform worse than Hynix A die - but will run in conjunction @stock XMP @1.4.
Which B-die kit (which product model # from the product page)? A Trident Z should be able to stretch out nicely but will be finicky possibly. Is it 2x8, 2x16? What initial timings, voltages, and resistances (procODT, cad_bus) are you trying (e.g. a Ryzen Master screenshot)? And your X570 Crosshair VIII Formula is good.
07-10-2020 12:06 AM
Rawson copied from asus owners club

Hi. I've got 2x kits of trident z. ones a samsung b and ones a hynix a. both kits are 16-18-18-18-38-58. The hynix will do 14-17-17-17-30-32, but the Samsung won't really do anything, no 16-16-16-16 either. Will I have to do step by step tuning on the Samsung? Is this motherboards overclocking support for RAM bad or is it bottom barley B die? I didn't expect B die to perform worse than Hynix A die - but will run in conjunction @stock XMP @1.4.
07-09-2020 12:23 PM
Maghook Just a quick reply for the moment. Fear, I have to read your post several times again
I just hoped for some timing correction tipps to prevent desync.

ASUS Strix 570 - daisy chain. No option to set different vDIMM for each channel.
IIRC than the E-Dies are on ch. A while B-Dies are on ch. B according to displayed bios spd information.
Speed is 3600 currently and stable with that settings so far. Currently unsure if I should really aim for higher. Maybe just for GDM off /w CR1 and a latency stable at or below 67? According to latest thaiphoon burner both kits are A0.
According to Membench I had better results with 256bytes interleaved than higher values, strange...
CADs are: 24, 20, 20, 24
ProcODT, RTTs currently all on Auto

Oh, uhm 3700X is currently capped at 55W PPT for effiency in addition with a 0,0875v negative offset.
Thanks!
07-09-2020 10:31 AM
Veii
Quote: Originally Posted by Maghook View Post
@Veii
Could you please just take a quick look over the following settings? Any advice greatly appreciated.

3700X with [email protected] MT/S (Corsair CMK16GX4M2B3600C18 LPX, 2 x (SR-)kits / one kit containing Micron E-die and one kit containing Samsung B-Die (I had some bad luck)
I read it, but many answers are on hold till i find more time to process everyone of them without prioritizing anyone
exceptions happen on short offtopic ones i can answer on the go or additional teaching material
My first question is,
~ can your board even split DRAM voltage between both of the Channels
I think it wouldn't work by the Daisy Chain Layout, but for example ASUS got creative on another iteration of Daisy Chain layout

You have several issues:
Micron E-Dies don't like voltage between 1.46-1.54~ volt, and after 1.6+ get far to hot
B-dies don't like voltage between 1.56-1.6v, but scale well between 1.42-1.46v
Soo your only range on which both work alright is around 1.38-1.45v

2nd issue,
Micron E-Die need CAD_BUS ClkDrv Strengh to drop GearDownMode,
while b-dies scale better at lower unless they are dual rank

3rd issue,
SCL range will be different, micron requirements will strongly slow down B-dies
And B-die requirements might not work on low end E-Dies (up to PCB)

Biggest issue,
Daisy Chain layout by itself
B-dies have no profit from increased signal strengthness and likely can be used as "slave" (dimm 1,3)
While Micron kits need that , just that are more sensitive to bad signal integrity
Overall VDIMM , cLDO_VDDG IOD and CAD_BUS ClkDrvStrengh are the key factors here
Daisy Chain Splits the main powerline into 75/25% - 25% for the slave set, while T-Topology splits it 50/50%
Having now two very opposite kits - that's gonna be fun

But the main key factor here, aside from the ICs
Is the PCB these things are on
Please make a photo-session of one B-die and one Rev.E
Important is that the IC location is visible from the side (further up or further down on the PCB)
And then on the side where the ICs are (the other side on Single Rank kits has just padding there)
Try to use some lightning from far away soo your Camera can pick up the traces - Dead center should already show the difference:
https://www.overclock.net/forum/1805...l#post28423902
3rd and 4th picture, maybe 2nd one but it should be a tiny bit further away

Optimally you'd want here the slave ~ B-dies to be A0 and Rev.E in this case be A2
A1 will be a bit of an issue but can work, but if B-dies are A2 layout or both ~ i wish you good luck

X2 kits need more current and love more current, you can go away with higher VDIMM on these and can put them on the main slot
While X0 kits don't scale well with high voltage, but aren't having much issues with bad signal integrity or weak signaling
A long-trace-layout , normal layout should usually like voltage and have a higher dropout rate, but funnily it's the opposite
A short-trace-layout X1 especially X2 kits love voltage but are sensitive to bad signal integrity
Quote: Originally Posted by Maghook View Post
Settings:
Spoiler!
Thank you very much!
You can follow this baseline from here and find the tRDWR & tWRRD guide at the end of the same post, or just here
The same post also has voltage templates, or you use the first source - which is on the same 4133 T-Force thread at the bottom of this post
Else people here are knowledgeable enough to help you with timings
These shouldn't be much of an issue after you try to equalize these kits - but you have to confirm first what they even are
Daisy Chain layout as great as it's marketed to be, will make you far more issues than T-Topology

tBL is 2 yes
tRRD_ ones will be crucial for deciding how long these dimms need between same bank groups and between different ones
Lower is beneficial, but always adjust tFAW accordingly
tWTR_ goes the same, except i would match tWTR_L to either twice or tripple tRRD_S

tWR you have to think SR and DR - SR kits will work with it between 10-18, Dual Rank logically 20-36 / just a double
Sometimes 4 dimms can have nearly the same requirements as to two dual rank dimms
same RTT requirements, same tRFC size, and also same tWR (write recovery) delays
What you can do, is use a double on some of the timings - some will just trigger later but not cause awkward desync's
Try to do the math for tWR with what works for 2xSR kits, and then just double this number if it ends up too low
Doubling that timing won't break tRAS ruleset, even when it overshoots
- but optimally you should try to hold both rulesets tCL+tRCD & tCL+tWR+tBL for tRAS
Quote:
tWR Ruleset:
Rec. = tRRDS + tWTRS
Alt. = tCL + tRTP
Alt. = tRAS - tRCD

Veii Rec. = tRTP *2
Veii Opt. = Clean non decimal divider of tRFC
tCL + tRTP , in case you have to unlogicaly bump up tRAS for stability
tRAS-tRCD, if you use some other awkward timings math, but going the other way like usually based on tRFC makes it more scalable
Then you can adjust tWR lower or double it if ever needed
One rule exists that it should be * 8ns, but that is only an ETA, as timings and ns delays scale by frequency
- no fixed numeral divider will be a correct ruleset
Try to keep tRAS to tRC (tRAS+tRP) transition clean, adding delay on tRC will mask timing user errors, but if it's not stable you have an issue somewhere
A cheating method there is just increasing tRP (p)recharge delay, and decreasing it to adapt for high vDIMM and lower tRC even further

It again ended up too long,
Don't use Interleaving size lower than 512 or go even higher, and keep both HW prefetchers on, same as Interleaving hashing
tCKE you want at 1 with GDM, and you want to keep IOD higher than CCD for 4 dimms - especially on your problem
Start with going to 2T mode with disabled GDM
If RTT, CAD_BUS, voltages and procODT are correct - it will let you without issues
if not, work on that one first

You didn't mention the frequency you go for too
cLDO_VDDP is for the memory controller, as long as you aren't using high procODT, there is no need to bump this beyond 900mV
Well as endnote , fix everything that is on auto except for Vcore
you don't need random variables and test voltages with Y-Cruncher (2-3 cycles all tests) + P95 Large FFT (2h usually)
07-09-2020 09:13 AM
Maghook @Veii
Could you please just take a quick look over the following settings? Any advice greatly appreciated.

3700X with [email protected] MT/S (Corsair CMK16GX4M2B3600C18 LPX, 2 x (SR-)kits / one kit containing Micron E-die and one kit containing Samsung B-Die (I had some bad luck)

Settings:
GDM: enabled (CR: 1) (well, with my low voltages I won't get GDM=OFF and CR1 proper without errors, but accepted that in 2 weeks of intense ram testing: vDIMM: 1,34v / vSOC: 1,0125v / cLDO_vddp: 0,781v (lower won't post, higher seems to bring no benefit at all to the table?) / cLDO_CCD: 0.950v / cLDO_IOD: 0,925v => trying to find efficient but still performant and stable sweep spot)
PDM: disabled
BGS Alt: enabled, interleaved @256bytes, Hw-prefetecher: enabled
tCL: 16
tRCDRD: 19 (->20 with GDM)
tRCDWR: 16
tRP: 16
tRAS: 36 (wouldn't it be better to go with 38 or 40 as tBL 2-4 has to be added to tRAS?)
tRC: 60 (could go stable for 58, with 56 getting errors - too low voltages I guess, but 60 seems okay for me. no clean division for 58 possible)
tRFCs: 540 / 401 / 247 (~300ns, clean divider to tRC=9. Once could go as low as 530 as hard border, then getting errors)
tWR: 16 (with 14 getting errors)
tWTR_S: 4
tWTR_L: 12 (10 was stable, but noticed you wrote once, that _S multiplied by 3 = _L)
tRRD_S: 4
tRRD_L: 6 (4 was stable but saw no improvement)
tRTP: 10
tFAW: 16
tCWL: 14
tCKE: Auto (BIOS sets always zero)
tRDRDSC_L: 4
tRDRDSC: 1
tRDRDSD: 4 (auto value from BIOS)
tRDRDDD: 4 ( I know, everybody is telling you to keep these on 5, but GDM would make them to 6?)
tWRWRSC_L: 4
tWRWRSC: 1
tWRWRSD: 6 (see above. would be 7, but with GDM should be 8 then, see no benefit from 1-5-5-1-7-7-0 over 1-4-4-1-6-6-0)
tWRWRDD: 6
tRDWR: 10 (reading ryzen calculator, B-die would need 9, while E-die would accept 8. But togehter i strongly need 10)
tWRRD: 4 (if I unterstand you correctly, these setting could also be set to '1', as 2 * tRDWR = 20 which is above tRCDRD=19. Is this correct?)

Thank you very much!
07-09-2020 04:39 AM
Veii
Quote: Originally Posted by Ronski View Post
I wondered that myself yesterday and found this posted over on Reddit
tRFC 2 = tRFC / 1.346
tRFC 4 = tRFC 2 / 1.625
https://www.reddit.com/r/Amd/comment...ould_i_bother/
If I leave my board on Auto it seems to work them out differently though.
Quote: Originally Posted by TheGlow View Post
Yea I've found the calculations since I posted, but as mentioned, the DRAM calc is great so not sure where its getting them numbers from.
The board works it out differently because it's a mess
(i think personally also a reason why PMU timing prediction is also still to this date incomplete)
DRAM Calculator by normal methods has a rounding error, but it's not the dev's fault
Frequency is inconsistent, it's not a whole value value
And so if you continue to use a fixed time divider from tRFC 2 -> 4 , the rounding error will exponentially be even more broken

Boards do autocorrect in realtime in the hidden, as timings are virtual long decimal values scaling by MT/s
Suggested tRFC by the Calculator factors in tSTAG and only works well for the whole set
Changing 1 little thing, makes the suggested lower tRFC value not optimal anymore
Advanced calculator tRFC field is also accurate, but i am not sure if 1usmus factored in that 3333 and 3334 spit out different tRFC2/4 - as used tRFCns math will change

tRFC Calculator exists for solely this purpose although it doesn't spit by hand tested values like 1usmus calculator
But it does spit out decently accurate estimates for correct tRFC
I wouldn't suggest to use this reddit published math, and take a look how i get tRFC 2 and 4
(you do calculate tRFC 2 and 4 individually and not with combined rounding from tRFC)
You will have rounding errors if you do it the opposite way, and you will get rounding errors if you don't put the correct MT/s frequency
You also won't get an accurate result from the advanced section in the calculator, if you don't put in an accurate tRFCns value
Which again, can be up to 11 decimals long
07-08-2020 11:03 PM
DeusM H guys, i have a small dilemma!


I have managed to boot at 3733cl14 and i dont think its stable because im unsure if i will damage the ram as my voltage is 1.5v


DDR4V: 1.5v
SOC:1.1v
Vddg: .950
VDDP:.900




Is this voltage safe or should i just give up on 3733cl14?
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