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  Topic Review (Newest First)
02-18-2019 10:35 AM
GTANY Hello, I have a kit similar to yours : 4x8 GB TridentZ 4000 c18 19 19 39.

I tried to change the 4 main timings to 17-17-17-37 and a few other ones but my system is not 100 % stable with these timings, because every timing must be changed. Consequently, may you give me your default values for the following timings, please (on Gigabyte Z390 Aorus Pro) :

t CCD_S
t CCD_L
t REFIx9
t XP
t XPDLL
t PRPDEN
t RDPDEN
t WRPDEN
t CPDED
t AONPD
RFR delay
t XSDLL
t XS offset
t ZQOper
t MOD
round trip latency (Dimm0/rank0)
round trip latency (Dimm0/rank1)
round trip latency (Dimm1/rank0)
round trip latency (Dimm1/rank1)
IoLatR0D0
IoLatR1D0
IoLatR0D1
IoLatR1D1
Rtt Nom (dimm0)
Rtt Nom (dimm1)
Rtt Park (dimm0)
Rtt Park (dimm1)
Rtt Wr (dimm0)
Rtt Wr (dimm1)

Thank you.
02-09-2019 05:41 PM
encrypted11 There are english captions for the first video, I referred to 3:00 onwards for the specific portion on memory topology.

Video #2, I've paraphrased the content on the comment #6 and that both QVLs of the Godlike Gaming and Extreme are referenced (T vs. Daisy chain on 2 DIMMs)
Toppc goes on to mention On-Die Termination's (of DDR4 ICs) in relation to T and Daisy chain layouts and that both slots on T need to be populated for extended OC margin for a "perfect signal" since there's a trace related to ODT on both A1 A2 and B1 B2 slots. That's unlike the daisy chain topology.

Video #3, just a video on "Dragon Alliance"... A couple of DRAM models with a stable IC supply (e.g. Hynix-A only, Hynix-C only) are picked from RAM vendors for demonstrating the benefits of daisy chain in a 2 DIMM config, MRC tuning were done on a number of these kits for an MSI certified auto overclock beyond XMP rating. e.g. A Corsair XMP-3600 kit with a designated IC running 4000MHz instead.

P19 onwards
https://download.msi.com/archive/mnu...king-Guide.pdf


Video #3 is related to another topic in his motherboard series on DRAM sorting from "module houses" (corsair, gskill etc) and how were the QVLs built on 4/6/8 PCB layer T-top 2DPC or 1DPC QVLs etc. Regardless, both Overall, Toppc and Raja referred to 4 DIMM being the ideal config for a T-topology motherboard for an extended OC margin.

Daisy chain on Ryzen: Crosshair VII Hero, on an article authored by The Stilt
https://www.io-tech.fi/artikkelit/te...-gigabyte-msi/


Elmor's C7H PDF extract on memory OC margin for this particular daisy chain board
02-09-2019 10:28 AM
jfriend00 Is there any English in those videos? I went to the 3 minute mark in each video per your suggestion and did not find any language I can understand. Perhaps some text describing what the point here is would be useful. Far too many link-only posts these days that don't offer any context for what this is about or even quote what they are responding to.
02-09-2019 09:39 AM
encrypted11 From [email protected], ASUS Engineer Bing L. and MSI's Toppc Lin
http://www.xtremesystems.org/forums/...y-memory-treat

3:00 onwards
02-09-2019 09:38 AM
encrypted11 Double.
02-09-2019 09:02 AM
jfriend00
Quote: Originally Posted by encrypted11 View Post
It's not about the limit of the memory controller here. Asus's advertised 4400MHz+ memory on 4 DIMM Maximus boards refer to a QVL entry with all 4 DIMM slots populated since these boards are on the T topology where 4 DIMMs will clock better than 2.

I do recall 4133MHz being the end of potential frequency scaling on these on 2 sticks.

MSI's Z390 boards are running daisy chain topology however, you'd have better 2 DIMM clocking headroom on those.
T-Topology does not mean that it will clock 4 sticks better than 2. It means it may clock 4 sticks better than a daisy chain motherboard will clock 4 sticks and in fact, it may not clock 2 sticks as well as a daisy-chain board will clock 2 sticks.

That's the idea behind T-topology, but I've also read a number of very technical articles that tout how daisy-chain can be tweaked (with timings) to be better for 2 sticks and just as good for 4 sticks vs. t-topology so some articles say it is more about the actual details of the implementation than it is about which topology is chosen.
02-09-2019 07:29 AM
Telstar
Quote: Originally Posted by encrypted11 View Post
It's not about the limit of the memory controller here.
With "limits" I meant to not ruin the cpu. Personally, I wouldnt go above 1,25 for long term use.
It has been said several times that 9xxx cpu have a great IMC and the limits are either the mainboard or the dam dies themselves.
02-09-2019 03:18 AM
encrypted11 It's not about the limit of the memory controller here. Asus's advertised 4400MHz+ memory on 4 DIMM Maximus boards refer to a QVL entry with all 4 DIMM slots populated since these boards are on the T topology where 4 DIMMs will clock better than 2.

I do recall 4133MHz being the end of potential frequency scaling on these on 2 sticks.

MSI's Z390 boards are running daisy chain topology however, you'd have better 2 DIMM clocking headroom on those.
02-07-2019 04:40 PM
Jaz11
Quote: Originally Posted by Telstar View Post
I believe it is mostly a motherboard limit. On top of this there is a silicon lottery among b-die chips (and this particular kit you got is known to be petty good).
You are at limits for daily of both vdimm, vccio and vssa, so I would eventually play only with subtimings to squeeze a little more in benchmarks and 0,something% in real world applications then call it a day [IMG class=inlineimg]/forum/images/smilies/smile.gif[/IMG]
Ok thanks. Yeh I think I will tighten trefi and tras and leave it at that for daily
02-07-2019 01:50 PM
Telstar I believe it is mostly a motherboard limit. On top of this there is a silicon lottery among b-die chips (and this particular kit you got is known to be petty good).
You are at limits for daily of both vdimm, vccio and vssa, so I would eventually play only with subtimings to squeeze a little more in benchmarks and 0,something% in real world applications then call it a day
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