Overclock.net - An Overclocking Community - Reply to Topic

Thread: [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread Reply to Thread
Title:
Message:

Register Now

In order to be able to post messages on the Overclock.net - An Overclocking Community forums, you must first register.
Please enter your desired user name, your email address and other required details in the form below.
User Name:
If you do not want to register, fill this field only and the name will be used as user name for your post.
Password
Please enter a password for your user account. Note that passwords are case-sensitive.
Password:
Confirm Password:
Email Address
Please enter a valid email address for yourself.
Email Address:

Log-in


  Additional Options
Miscellaneous Options

  Topic Review (Newest First)
08-11-2020 02:02 PM
betam4x I bought some Micron E-Die CL18 DDR4 3600, does anyone know how well the chip performs/if timings can be tightened? Thinking about putting the hynix RAM in my wife's computer since my motherboard doesn't play all that nice with it.
08-11-2020 06:53 AM
Veii Uhm 3600 CL14 requires around 1.42v
CL13 around 1.56v
CL12 around 1.68-1.73v

3800 CL14 ~ 1.48-1.52v
CL13 ~ 1.6
CL12 ~ 1.72-1.76v
1.8 looks "reasonable"
Aroun 1.7~ is about the range for CL12, if your B-Die doesn't get unstable after 1.56v

Hynix MFR 3200 CL15 ~ 1.48v
CL14 ~ 1.56v
3400MT/s CL14 ~ 1.62v
08-11-2020 06:47 AM
Veii
Quote: Originally Posted by chitos123 View Post
@Veii
What about 4x SR alt? 4466 or 6688, Rec is 5577
(2x, 4x DR is 4466,5577)
4x SR works well with 1-4-4-1-6-6, but that was computerbase testing
Both deliver good results, keep 4-4-6-6 for 4 dimms or 2x DR.
Will update once i see better reasons, it needs testing across the whole range with SiSoftware Sandra Multi-Core effiency test (latency curve)

Quote:
Change Test 0,3 to tRCD =(RD+WR)/2
=This Wrong thought from "tRCD_RD >= tRCD_WR"

Looking at your quote, It's different from the rules I used to know
"tRCD_RD >= tRCD_WR" -> "tRCD_RD < tRCD_WR"

So. IF that happened
I'm not sure what to do "tRD_WR <= tWR_RD"
tRP timing is very variable, up to how much VDIMM you give
GDDR6 (micron and samsung, both identical) and DRR4 use tRP +1 of tRCD, to cover for recharge
But cells discharge Time depends on heat, voltage amount, cell quality, PCB quality
You can only estimate it, where at best it is always = highest tRCD ~ covering highest delay.
Meaning, it will pause and let this time elapse for recharge, the shorter tRP ~ the higher the chance of not enough charge and data "corruption"
Higher heat increases discharge, but higher VDIMM increases overall charge. Too high vDIMM will overcharge anything above rated 1.35v will overcharge. Soo sometimes less is better
If you freeze it, it will accept higher charge, if cells are hot they will leak voltage faster ~ only way to "degrade" memory

By this same principle i use average tRCD delay on the whole picture.
tRP = tRCD_WR is the absolute minimum = correct
BUT, this works only for short time and will someday choke because tRCD_RD difference can be big. People push tRCD_RD to cover for slower IC. Pushing tRCD_WR down is an AMD exclusive thing, and technically identical to pushing only one tRCD down = average tRCD
Using average tRCD for tRP as baseline is a good method.
Later you still can lower tRP if you overvolt it further or increase Impedance to lower tRC

Just as 1usmus mentioned, tRC is also AMD exclusive and a "time arrangement"
We use tRC to cheat and finetune perf a bit, but mostly because i use tRFC Discharge ETA formula, which requires accurate tRC for it to work.
all goes around average delay, autocorrection will happen anyways it tRC is too short or tRFC is too low (tRFC will be postpone)
Quote:
Only tWR_RD 1 allowed?
you can use avg RCD delay also for tWRRD.
i always use 4* X = < Avg tRCD delay.
Same should apply to intel:
tRRDD, result < or = 4*X of tRCD.
need to check the intel thread for testing rabbits to check tRRDR (tRDWR) and tRRDD (tWRRD)
But if result is > tRCD_RD it will not post. It also makes issues if you end up with tRDWR 9 and tWRRD 6, only one can be high not both.
SCL for multiplier sometimes works sometimes doesn't on tWRRD. Rule of thumb is 4* X = < tRCD
(which RCD you use depends, avg works well so far. Wrong value only will prevent post)
Quote:
Will change "tRCD_WR=tRP" to tRCD =(RD+WR)/2
+Test 1 is worng calculation So Fix That too
Please do, this is better . tRCD_WR=tRP will work once, but very likely will drop out after long testing sessions. Ruleset baseline is = tRCD (not WR) or +1. GDDR6 uses +1

Quote:
I see,
Time Remove manual tRC and change to tRFC =tRC*X
+EDIT Does tRC*X mean X isn't tRTP ?
then ahhhh. ummm.
OK. all my thought is wrong again

I have to learn baby steps Again !
Can you tell me how to calculate tRFC ?
X is not tRTP
tRTP has to be inside tRFC range, as clean divider, because tRFC can be moved around and postponed 9 times inside whole tREFI range.
tRFC is a fixed delay, but when it will trigger is variable.
Soo i use exact timing of tRC with *6 according to this discharge graph

~ cloned from Donghyuk Lee's DDR Heterogeneity Research Paper
*6 works well on Single Rank. i've seen people rarely get *7 to work
My focus is half tCL delay, but sometimes result get in half decimal.
tRFC is a big topic and i need more research into it getting *5 + tSTAG to work

tRTP and tWR have to be inside tRFC range as clean dividers. tRFC size doesn't matter much
Both either are rounded up to even values with GDM, or are odd values without GDM.
Exact divider is more important here, maximum down to half divider (XX.5 value)
This means, even when tRFC is postponed on timings error or heat discharge issue, it won't crash because it remains still accurate after being postponed.
Just baseline ruleset, but not key ruleset
tWR = tRTP *2 is the same thing, clean divider is more important, *2 of tRTP not so much - they can be uneven as long as they are clean dividers
Only goal is that when tRFC get's shifted, it remains accurate and the user doesn't only go for lowest possible latency.
Too much autocorrection happens to predict every scenario, this is the reason for my ruleset. tWR calculation ruleset are accurate, all of them

Quote:
Have a question,
Is there any other rule to calculate tWR ?
Rec. =tRRDS + tWTRS
alt. =tCL + tRTP
alt. =tRAS - tRCD(RD+WR)/2
alt. =tRCD(RD+WR)/2
alt. =tRP
Veii Rec =tRTP *2
I use 2 rulesets atm:
Main rule is clean divider of tRFC_
(there can be many results, 4-5 including 4 decimal one like .5=1/2, .25=1/4, .625=1/8th, .8175=1/16th results)
Reason for this is that tRFC on it's own can go down to 1/32th accuracy. On 32 tRFC = 32,16,8,4,2 value, as negative of positive steps
2nd rule is:
Trying to match up tRAS by going tCL+tWR+tBL (2) according to Donghyuk Lee Research and "cheating" method for lowering tRAS
result still can be 2 values as options (optional)
3rd rule if still options are left
tRTP*2, but high tWR shows shows big stability impact.
Rule 3 is only used for baseline calculation but often if you have tRTP 8, you can use either tWR 16 or 12. Then i strongly prefer 12 because the perf impact is big, and because i want tRAS low
(baseline calculation ~ still trying to figure out 1usmus's method of tRCD+tBL)
Quote:
this too
tRP =tRCD_RD
tRP =tRCD(RD+WR)/2
tRP =tCWL or tCL (Not sure about this)
Never used tCWL for this math, i don't know i'm sorry.
tRP = RCD biggest value (stability)
tRP = avg tRCD value if you tRCD_WR is < than tRCD_RD
using always avg RCD as tRP makes it always correct. Using only tRCD_WR = tRP will make issues after time, because of cells discharge by heat. Manual tRP should be an option till we have a big dataset of how much VDIMM requires which IC before discharge issues happen

Quote:
Error 8 suspect is tRRD_ & tWTR !
3,4,5,6,14,15= mirror move, But Difference solution
Thank you for spending your time for me

Sent a cup of coffee.
BTW, i don't know when you'll get it..
Cup arrived, was in a coffee shop to process all mentions before you send it
seeing it slowly as daily work haha

Atm i save for an ITX B550 board, but they all are expensive (150-180€)
Maybe middlestep will be biostar, but ugh i don't want to work on their bios
Soo my eyes are on the Phantom Gaming ITX/AX, as the Impact is too expensive

Here something fast to get both correct:
tRFC ~ =((tRCns*X)*MT/s)/2000
tWR ~ =tRFC/(tRC/2)
tRTP ~ =tWR/2 or just =tRFC/tRC
EDIT: non of this math seems to work for custom tRFC 288 on CL14-tRC42 from DRAM calculator. But Yuri also use tRTP 8 which is a clean divider, same as tWR 12 is a clean divider
08-11-2020 06:28 AM
nick name
Quote: Originally Posted by rent0n View Post
I'm already sitting on 61.9ns, but I'm going to check your settings out and see if I missed something. Cheers! )
It's like you said -- the higher tRFC makes the lower CL moot.
08-11-2020 06:18 AM
rent0n
Quote: Originally Posted by nick name View Post
You could try this:

I'm already sitting on 61.9ns, but I'm going to check your settings out and see if I missed something. Cheers! )
08-11-2020 06:15 AM
nick name
Quote: Originally Posted by rent0n View Post
buildzoid did manage to reach similar or even better settings in his preview of the X570 Taichi's memOC capabilities, but I guess there is no room for comparison between that motherboard and mine. Furthermore, he used a 3700X. I've also seen some HWBOT submissions with a Zen 2 and 3800/CL12 B-Dies, but no details on all the settings. I have tried raising the ProcODT and the ClkDrvStren-CkeDrv, same results. The reason I asked is mainly because I'm not familiar with all the secondary and tertiary timings, and had the feeling I might be able to boot at CL12 after tweaking some settings.
You could try this:
08-11-2020 06:03 AM
rent0n
Quote: Originally Posted by nick name View Post
The only time I can remember anyone using CL12 was during one of Bearded Hardware's videos. He, though, was leaving much of the other timings on Auto (including tRFC). So I think it's likely as you've discovered -- you need a higher tRFC to reach such a low CL.

I haven't been able to boot CL12 either on my 3600C15 or 4400C19 kit. I didn't back off tRFC in my attempts.

buildzoid did manage to reach similar or even better settings in his
of the X570 Taichi's memOC capabilities, but I guess there is no room for comparison between that motherboard and mine. Furthermore, he used a 3700X. I've also seen some HWBOT submissions with a Zen 2 and 3800/CL12 B-Dies, but no details on all the settings. I have tried raising the ProcODT and the ClkDrvStren-CkeDrv, same results. The reason I asked is mainly because I'm not familiar with all the secondary and tertiary timings, and had the feeling I might be able to boot at CL12 after tweaking some settings.
08-11-2020 05:49 AM
nick name
Quote: Originally Posted by rent0n View Post
Since I got no answer in the IF thread - here - I'm going to ask the same question in this thread: has anyone had any luck pushing Samsung B-Dies to 3800MHz CL12 on a B450 board? I have a F4-3600C16D-16GVK Kit, July 2020. According to Thaiphoon each module has an A1 10-layer PCB, but I'm pretty sure it's an A2 layout, so that reading should be wrong. I am running a Ryzen 5 3600, which can go as high as 4.6-4.7GHz on air for benchmarking and so far the memory sticks have been running at 3800MHz (1900MHz FCLK) 14-14-14-28-1T-42-260, GDM off. I haven't had any luck booting at CL12 for a benchmark even with GDM enabled and voltages between 1.65V-1.8V, so I'm thinking either the bin of the kit is not that good, or the mainboard is just bad at memory overclocking, it's only a MSI B450 Tomahawk MAX. If anyone has any experience or suggestions, I would be glad to hear them.


In addition:

1.1. - I managed to boot at CL12, but tRFC has to be above 400 in order for it to work, which results in worse latency and reads
1.2. - for me the AGESA 1.0.0.6 made little to no difference regarding memory OC

Edit: Going to attach a screenshot with my settings later today.
The only time I can remember anyone using CL12 was during one of Bearded Hardware's videos. He, though, was leaving much of the other timings on Auto (including tRFC). So I think it's likely as you've discovered -- you need a higher tRFC to reach such a low CL.

I haven't been able to boot CL12 either on my 3600C15 or 4400C19 kit. I didn't back off tRFC in my attempts.
08-11-2020 05:45 AM
infraredbg
Quote: Originally Posted by Veii View Post
I see
I think people would start to be worried about that "variable" MCLK, FCLK, UCLK ~ haha
It's good to have it
Also great work ~ very very useful !
just hope another PSP firmware update won't kill RTT readout
Speaking of, is this AGESA 1005/1006 with the new update ?

Do you think , you can somehow request from FIT the current variable VDDG ? the exact split in IOD and CCD ?
I think it lacks a sensor, but FIT should be aware of what is applied
I have dumped all the possible values in the PM Table, but could not find a separate IOD and CCD. Thought I've found it at first, but that value stays fixed and doesn't change when I tweak VDDG voltages.
I'm testing on Crosshair VI Hero with latest bios (AGESA 1.0.0.6). It's possible to add those other values you've requested.
Currently there's a problem with first launch of the app after a reboot which I'm trying to solve.
08-11-2020 05:13 AM
rent0n Since I got no answer in the IF thread - here - I'm going to ask the same question in this thread: has anyone had any luck pushing Samsung B-Dies to 3800MHz CL12 on a B450 board? I have a F4-3600C16D-16GVK Kit, July 2020. According to Thaiphoon each module has an A1 10-layer PCB, but I'm pretty sure it's an A2 layout, so that reading should be wrong. I am running a Ryzen 5 3600, which can go as high as 4.6-4.7GHz on air for benchmarking and so far the memory sticks have been running at 3800MHz (1900MHz FCLK) 14-14-14-28-1T-42-260, GDM off. I haven't had any luck booting at CL12 for a benchmark even with GDM enabled and voltages between 1.65V-1.8V, so I'm thinking either the bin of the kit is not that good, or the mainboard is just bad at memory overclocking, it's only a MSI B450 Tomahawk MAX. If anyone has any experience or suggestions, I would be glad to hear them.


In addition:

1.1. - I managed to boot at CL12, but tRFC has to be above 400 in order for it to work, which results in worse latency and reads
1.2. - for me the AGESA 1.0.0.6 made little to no difference regarding memory OC

Edit: Going to attach a screenshot with my settings later today.
This thread has more than 10 replies. Click here to review the whole thread.

Posting Rules  
You may post new threads
You may post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off