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Thread: NEW!!! DRAM Calculator for Ryzen™ 1.7.3 (overclocking DRAM on AM4) + MEMbench 0.8 (DRAM bench) Reply to Thread
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  Topic Review (Newest First)
07-14-2020 11:58 AM
Ronski
Quote: Originally Posted by helsyeah View Post
@Veii mentioned something about boot issues being tied to ProcODT/CAD Bus.



You might need to bump ClkDrvStren up to 24/40 or make other general CAD_BUS adjustments to clean it up.
Thanks for this info, here's the scores you asked for in your PM. No idea why Maxxmem2 doesn't show my system spec or latency - I've contacted the author.

Edited to add last nights results, sub 104 second Membench, 1 error in 20 cycles of TM5
07-14-2020 11:46 AM
algida79
Quote: Originally Posted by Veii View Post
The calculators set probably is more stable than what i can suggest
Yuri's presets where all pre-tested and confirmed to work
I can suggest you something on an edit, or remake the whole set
But would need to know your tRCD limits, remind me your IC and PCB layout & maybe what SCL you have tested
tRCD depends on the kit, what is easy to run for someone else, might not even post for you

Else , have you figured it out till now ?

Thanks @Veii but I have abandoned the idea of 3600MT/s altogether. I tried to calculate the possible combinations and I don't think I would finish testing all of them in this life!


Spoiler!





I am now concentrating on 3533 tuning where I am having some encouraging results already. Photos of the kit:







Gradual tightening is still in progress, so far made it to this config:
Spoiler!


passing 30 cycles of TM5 last night. By the looks of things, tonight I will be testing this config:
07-14-2020 08:56 AM
Veii
Quote: Originally Posted by DeusM View Post
Hi guys,
@FlyByU i have gotten to 3800cl16 with these settings. First shot of testmem5 25 cycles there was 0 errors
The second run i just completed showed me 2 errors. Error no3 and error no4
If anybody can help what do these errors mean? More voltage? soc? loosen timings?
Non of either,
Error 3 & 4 by checking the MT.cfg - are MirrorMove errors
That set shows tRFC 2 issues and this tRFC "auto predicted" ? is wrong.
tRFC is so far always even
as tRFC stepping are 32,16,8,4,2 , ~ 319 would be plain wrong
Also tWRRD should be 4 , as 4* X = 16 , 4 fits (it should undershoot but not overshoot)

Quote: Originally Posted by LuckyBahstard View Post
I have a question then, for the group here... so have you found PBO to be the difference in stability? (that's a yes, I'm sure) And, have you found a way to work it back in, but perhaps with boost limits or offsets to help prevent the chance of mem errors?

I assume this is what gave me a random Sony (Magix) Vegas error during video editing, even though I thought I had a stable 3733. I could have just turned off or tuned PBO and probably been fine.
It does, as when the memory controller stress increases, so does procODT
when procODT increases, vSOC overall needs to be adjusted higher
vCore plays a bit of a role too, soo as PBO does increase overall and average allcore voltage - it can happen that on an allcore, it takes too much voltage

You can drive against it by limiting TDC & EDC
EDC especially always peaking at 100% will limit allcore voltage
although it will already limit it's range, even when you meet the 80% target
Seems to be, % stress to SMU limits go hand in hand and are predefined after which step, by how much should it should drop

Quote: Originally Posted by algida79 View Post
@Veii thank you very much for your suggestions. I will work on them and report back. What changes can I make to the timings before I start playing with new combinations of ProcODT, CAD_BUS, RTT to ensure timings are 100% not the issue? Could you suggest a loose but correct set of timings for this purpose? Current set is the calculator's Safe profile for 3600MT/s.
The calculators set probably is more stable than what i can suggest
Yuri's presets where all pre-tested and confirmed to work
I can suggest you something on an edit, or remake the whole set
But would need to know your tRCD limits, remind me your IC and PCB layout & maybe what SCL you have tested
tRCD depends on the kit, what is easy to run for someone else, might not even post for you

Else , have you figured it out till now ?

Quote: Originally Posted by zsoltmol View Post
Hi @Veii ,
Maybe I have traced down my issues to memory timings. And I would like to request your help. You share a lot of information in your posts, but I'm a bit lost to properly understand them. Memory holes, voltages, MT/sec, etc :-)

Here is my current setup:
CPU SOC with negative offset of 0.01250v (HWinfo report: 1.088 idle, 1.072 multi core load)
4x8GB Samsung b-die single rank memory in Asus C8H
PBO: enabled with motherboard limits, Scalar 1X, 0MHz uplift
What voltages do you suggest to set, I want to avoid I give too high voltage to parts. Can I decrease some of them?
I'm sorry, it's quite a lot of different information
But you can learn about the memory hole issue back then, on 1usmus's main page of this thread "cLDO_VDDP single error"
and i suggest to read the old Techpowerup plus current Guide of him.
It shares a lot of maybe complicated but useful information

When it comes to voltages, you know your board is Daisy Chain correct ?
Do you know the PCB of your dimms ?
I would suggest to figure that out, when you want to run run 4 dimms on Daisy Chain, where the signal is split 75/25%
If you have 4x A0 PCBs, it doesn't matter
But if you have 4x A2 PCBs, you'll have a hard time
At best figure out which PCB these kits are on, to optimise placing a bit
It would be even better if you can spare the time to figure out what the lowest voltage of each set is, at which of both will have negative scaling beyond 1.46 VDIMM

About voltage presets
It's not thaat much of an issue these days, but try to keep cLDO_VDDP to a fixed known to work voltage
900mV is known to work well up till 1900FCLK,
pass 950 only when you go beyond 1900FCLK
We know that 900 works across the whole range, but we don't know if 910 works across the whole range
For success, on 4 dimms - push more IOD and increase ClkDrvStrengh under CAD_BUS / in order to lower procODT more

cLDO_VDDP 900mV
VDDG CCD 950mV
VDDG IOD 1000mV
vSOC 1075mV
^ for vSOC , if you want to keep it variable - adjust loadline to match 1075 and never fall bellow 1050 in any case

The global negative offset might cause you issues under low voltage lows, soo be sure to doublecheck vdroop on AVX2 tests
For example the whole y-cruncher test suite, and prime95 LargeFFT

Quote: Originally Posted by Dollar View Post
So today I decided I wanted to see how things performed with two sticks instead of the usual four. This led me to discover the sad fact that Patriot sent me a mismatched PCB kit .... I bought two 2x8 kits of the same 4133 bin Viper Steel. Three of these sticks have A0 pcb but one has something different.... It appears to be the same A2 pcb shown on the 4400 viper steels

So yeah, Patriot sold me a kit with one A0 stick and one A2 stick in the same package. @Veii or anyone else, how does this affect overclocking? Three A0 sticks and one A2 stick.... Is it worth begging Patriot for an RMA? They all work so I'm expecting to get denied.
If they missmatched one set of kits, RMA it
If you sadly bought it dimm by dimm - sorry but they might or might not accept

Viper is pretty chill usually when it comes to RMAs,
You might even be able to RMA the whole set and get only 2 dimms of higher capacity
Depends, but yes RMA
Memory goes into groups, same as bank group swap will adjust work
the difference between A0 and A2 big, you would need to overvolt the whole A0 set just to match A2 requirements
If you can , RMA - if you can't, try to sell it or buy a single 4400 C19-19 kit and sell it as a set of two A2's
Then later buy a single 4000CL19-19 , and it will be A0

4x A0 is easy to work with, 2x A2 and 2x A0 is alright under daisy chain
But 4x A0 is easier even on T.Topology , although 4000MT/s is around peak limit before the PCB starts to be an OC issue

Quote: Originally Posted by helsyeah View Post
I'm pretty happy with that so far.

@Veii (or anyone else for that matter!) I have some specific questions:
  • Is there any way to lower vSOC by tweaking other values? (I don't fully understand how the voltages/impedance relate to each other)
  • Can tRD WR be reduced back to 8 by adjusting other timings and still obtaining a performance boost?
  • How would I go about (if possible) stabilizing lower SCL values since I'm seeing errors/crashes going below 4?

I'll say this is a fun, although complex! project, tons more for me to learn!
vSOC you can only lower if procODT is low
procODT you get low by working with CAD_BUS (lower everything except ClkDrvStrengh) and maybe increase RTT values till you can get away GDM
2T GDM even if it's slower will only work, if CAD_BUS & RTT is correct

Also lower the main voltages,
you need to adapt cLDO_VDDP and VDDG if you want to have vSOC moving near 1050mV
Also i recommend to enable UncoreOC mode , soo the CPU doesn't autocorrect custom voltage sets, visible here
If you want to spare the time, you can try to play with "CAD_BUS Timings" and increase memory voltage
They change according to frequency, between 50-60 is useful
It does define the signal cut time, and is useful if you rock unstable kits under very high VDIMM
It will add latency, but is useful when you run ClkDrvStrengh of 120ohm
This should help you hit higher FCLK, but needs a lot of testing work to figure lowest correct CAD_BUS Timing

Else lowering thermals works by finetuning TDC, EDC values
There is no need to go too low on voltages, if your main goal is saving power

Quote: Originally Posted by DeusM View Post
I think my problem is how hot my ram is getting in gaming and under load.
Up to 46.1c and i was reading that above 40c it will throw random numbers which will explain why i can run TM5 perfect one day and not the next.
Example. 3 nights ago i had 0 errors. 2 nights ago i had 2 errors on number 3 and 4 so i gave it a bit more voltage and last night it have me errors on 1 and 15.
3 tests 3 different results.
Im going to buy a small 40mm fan to blow directly over the ram to see if it will help.
Yes it could be thermals related, but you could just change the set of timings
Increase tRP and maybe lower tWR soo tRAS changes, and tRC remains
Increasing tRP will combat high thermals, as it will take longer to (p)recharge cells, and not timeout

Error 3,4 remain timeout issues, but have you fixed tWRRD at this post up to 4 with tRDWR 9 ?
You should be able to lower even tRDWR to 8 , while using tWRRD 4
tRFC 2 and 4 was wrong, but i think you did fix it already ?

B-Dies overall get unstable after 42c
It's a chance to be unstable, and up to timing harshness, even at 48c they won't get unstable
Keep tRFC correct, and increase tRP is you have voltage/heat issues
It's recommend, if you can't run GDM Disabled with 2T, to finetune first CAD_BUS
You might be able to run 30-20-20-20 - this will also lower heat across the whole board

Quote: Originally Posted by Awsan View Post
Tried 60-20-20-20 and it gave an error in the first 2 mins in TM5
Between 60-20-20-20 and 60-20-20-24 is a big difference
You can see if 40-20-24-24 runs, or 60-20-24-24 with lower procODT
07-14-2020 02:01 AM
DDSZ
Quote: Originally Posted by Solohuman View Post
Got it, thanks.
Here's the readout for my new sticks.
Now to tune this up as far as possible for daily use.
Be aware that I have Trident Z kit with the same XMP profile, which is reported as CJR in the Thaiphoon Burner, but it is actually JJR, so not all Calc parameters will work. There is a sticker on the stick, mine says 04266X8820J, where J means JJR. From my observation JJR needs bigger tRFC, so take care
It would be cool if someone here with JJR could share their experiences, especially with dual-rank sticks
07-14-2020 12:11 AM
FranZe
Quote: Originally Posted by mongoled View Post
Yup its a great result and TM5 stable, I dont know if it agesa ComboAm4PI 1.0.0.6 or running tRCDRW at 8, but I could never get those settings stable before when using tRDCRW of 14 on previous agesa that was available for the BIOS which I think was 1.0.0.4.

Will have a look at the thread you posted

I must admit that the 97 sec Membench i was showing earlier wasnt TM5 stable (because of 258 trfc), and i do like to pass memtests. 301 trfc is TM5 stable. I like to do at least 50 runs with TM5 and Karhu over night. I also like to stay under or right over 1.5v on the memory. I'm on agesa 1.0.0.4 btw

07-13-2020 09:26 PM
Solohuman
Quote: Originally Posted by rares495 View Post
16GB sticks are usually dual rank so you can just select Rank: 2 in the calculator.
Got it, thanks.
Here's the readout for my new sticks.
Now to tune this up as far as possible for daily use.
07-13-2020 08:53 PM
rares495
Quote: Originally Posted by Solohuman View Post
I notice this DRAM calc does not give option to tell it if one has either 2x8GB or 2x16GB kit. I'm presuming if one marks dual rank sticks for 32GB kit, it will pick it up??

16GB sticks are usually dual rank so you can just select Rank: 2 in the calculator.
07-13-2020 08:30 PM
FlyByU
Quote: Originally Posted by DeusM View Post
Somebody can correct me if im wrong but i don't think for 2 sticks it will change.

From what i have read and my own conclusions it seems to stem from the Daisy Chain.

eg if you have a ram stick that is "stronger" it would be better in the primary position? i could be totally wrong about this.

but its also why iu think 2 sticks wont matter at all.
If that is the case, and based on the previous image: I have them in the best slots. I'd just need to swap positions and see if it improves...
07-13-2020 08:20 PM
Solohuman I notice this DRAM calc does not give option to tell it if one has either 2x8GB or 2x16GB kit. I'm presuming if one marks dual rank sticks for 32GB kit, it will pick it up??
07-13-2020 03:28 PM
helsyeah
Quote: Originally Posted by Ronski View Post

Once stable I'll still need to sort out my reboot issue, as in it doesn't reboot, just sits there doing nothing, but turning off and on again always boots fine.
@Veii mentioned something about boot issues being tied to ProcODT/CAD Bus.

Quote: Originally Posted by Veii View Post
....
Bad procODT would cause only full post issues, cold boot and warm boot issues belong to CAD_BUS
....
You might need to bump ClkDrvStren up to 24/40 or make other general CAD_BUS adjustments to clean it up.
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