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Thread: NEW!!! DRAM Calculator for Ryzen™ 1.7.3 (overclocking DRAM on AM4) + MEMbench 0.8 (DRAM bench) Reply to Thread
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  Topic Review (Newest First)
05-31-2020 10:38 PM
rush2049
Quote: Originally Posted by Veii View Post
Ooh this is interesting
But why did you pick Dual Rank then ?
8x8 = 64gb
Top ones are A0 bottom ones are A2
Push for sure 40-20-24-24 CAD_BUS
And put the 4xA2 dimms as the main ones
Is your board daisy chain or T-topology

EDIT:
I don't know if the board allows you
But push 20mV more on the A2 kits, if not even 30mV
Instead 1.46v on A0 for example 1.48v on A2
I actually had CAD_BUS on auto..... which was doing 24-20-24-24 according to ryzen master.
And my ram was running at 1.35v


To apply your suggested changes I upped the voltage to 1.38v
Slight improvement....

So what would the next jump be?

05-31-2020 09:27 PM
Veii
Quote: Originally Posted by rush2049 View Post
Four of my sticks are the first image.

Four of my other sticks are the second image.

Not ideal I know, but I ordered the exact same part number and got what I got. I would love to have all A0... but I wasn't willing to buy them over and over to return them.
I will try your suggestions.
Ooh this is interesting
But why did you pick Dual Rank then ?
8x8 = 64gb
Top ones are A0 bottom ones are A2
Push for sure 40-20-24-24 CAD_BUS
And put the 4xA2 dimms as the main ones
Is your board daisy chain or T-topology

EDIT:
I don't know if the board allows you
But push 20mV more on the A2 kits, if not even 30mV
Instead 1.46v on A0 for example 1.48v on A2
05-31-2020 09:19 PM
rush2049 Four of my sticks are the first image.

Four of my other sticks are the second image.

Not ideal I know, but I ordered the exact same part number and got what I got. I would love to have all A0... but I wasn't willing to buy them over and over to return them.
I will try your suggestions.
05-31-2020 09:04 PM
Veii
Quote: Originally Posted by rush2049 View Post
Anyone have suggestions regarding the subtimings? I am trying to get the latency to be better. I've followed the recommended voltages (middle column) on the dram calculator, but I don't have any qualms about going higher. (water cooled ram).
You've pretty much maxed out your possibilities without some big changes
These timings are actually very well made
Did you use CAD_BUS 24-20-24-24 or 40-20-24-24 ?
Asking because of Signal Integrity

Oh on sTR4 you can go decoupled mode without negative effects
it does scale up til 4200MT/s
Only thing that stands out is 6x tFAW - sixth activate time window, while DDR4 doesn't allow more than 4x tRRDS to pass through the activate time window. it does timebreak and refuse to accept any other cell-activate tries
Wonder why 6 where used even when you try to stack and try to hit faster refresh, it shouldn't work with a fixed limit i hope it's just a calculator bug, as this looks awkward
Maybe it's just higher soo cells recharge in time, but tRP is high to begin with - making no sense to waste delay there

Are you actually sure that you have X0 PCB ?
The 3600C15 ones usually are A1
Now it's a bit stupid with a block on them to check PCB revision

Try that:
05-31-2020 08:47 PM
Veii
Quote: Originally Posted by bigfootnz View Post
Hi Veii, can you please explain why you are recommending to have 50mV difference between CCD and IOD? As by any version of ryzen calculator is setting them equally just like by default on my MSI ACE board? Thanks
The calculator does include that offset already
Early on the voltage inside the calculator where factoring in only one VDDG control voltage
I do split them now, but they have playroom
Usually you did:
VDDP + 50 to 100 / or 75 to 150mV stepping
* the key is to be at least 50mV , but the issue lies that vSOC at 1000mV won't be enough
** yet the ruleset remains VDDG+50mV for vSOC

Soo double stepping has to be used
What you use doesn't play a big role, while it does play a tiny one ~ more to it later
Because nearly always double stepping is used from VDDP to VDDG, it always was factored in the split covering IOD and CCD
I split it, just for accuracy sake and because we focus on fixing or pushing specific parts ~ giving it more voltage
Fixing IOD on bad boards to cover up for bad PCBs and so pushing memory OC
Or pushing CCD higher to help with per CCX OC on quality boards without decreasing Signal integrity by pushing more voltage for IOD (in this case even lowering it a bit)

It's just tiny optimization parts , something small yet with important effect for better signal integrity
Lower voltage always is key for higher FCLK and MCLK, because better signal integrity is important
But picking random voltages has issues - because the ryzen already does have a stepping ruleset
Breaking that is allowed by enabling UncoreOC mode inside AMD OVERCLOCKING
But why not just hold to their research and play with AMDs rulesets
You have to have at least 46-48mV headroom over VDDP->VDDG and the same goes for VDDG->VSOC
Just pushing VDDP to cover up for too low VSOC is stupid , we need less VDDP not more
Quote:
What you use doesn't play a big role, while it does play a tiny one ~ more to it later
This is now important
If you've followed 1usmus's iOC guide, per CCX/CCD OC guide
You might find some oddness in the frequency scaling
It actually does scale a bit between per CCX
I am not fully sure why - but i've noticed something odd across the whole 3rd gen lineup

Taking for example a 3600
The sample i've played with was pretty much maxed out on sillicon boost , it couldn't sustain more than 4.1 allcore or 4.2 boost
While the "golden cores" where wrong on RM and also wrong on HWInfo, even tho CPPC was functional after the RM wipe
The only thing that allowed it to be pushed higher without changing boosting behavior was by using a specific frequency difference
I've tried 40,42 / 40,43 / 41.5,42
It always crashed on AVX2 renders
Couple of samples already showed that it had to use a pattern, also for frequency
a difference between CCX with a frequency of 50mhz was not stable, same as a difference of 125mhz was not stable
A difference between CCX with a frequency of 75mhz was perfectly stable and we where able to push it even up to 100mhz difference between them

Anything higher or lower than 100mhz was pretty much a worse result
While 75mhz later sadly crashing under more heavy workload
Spoiler!
The result i think was quite bad, as TV was running too and a thread ACPI/CPPC analytic tool

Usually an iOC guide from 1usmus a rewrite was in plan
But i needed to collect couple of more data with dual CCD units, soo i didn't talk about it much
Tho there are some scaling patterns - soo i try to work with AMDs ruleset and split it
Else it will do it itself, and when i tell people to enable UncoreOC mode ~ it's good for it to be split as you can't rely on the board to split it afterwards
You will waste current and lower signal integrity, as this current has to go somewhere - when you push more than it's needed
05-31-2020 08:37 PM
rush2049 Anyone have suggestions regarding the subtimings? I am trying to get the latency to be better. I've followed the recommended voltages (middle column) on the dram calculator, but I don't have any qualms about going higher. (water cooled ram).
05-31-2020 07:50 PM
bigfootnz
Quote: Originally Posted by Veii View Post
VDDG IOD is a tad high
VDDP 950
VDDG CCD 1000
VDDG IOD 1050
VSOC 1150
fits,
All depends on what stepping you use, as 50mV has to be the minimum used between these
Usually VDDP 900, CCD 950, IOD 1000, vSOC 1100 would fit well
But maybe CCD one will be too low for your perCCX OC
you could use 75mV stepping too
VDDP 900, CCD 975, IOD 1025, VSOC 1100
vSOC doesn't have to be double stepping - but these 4 voltages have to follow some kind of pattern and never be under 50mV appart
https://www.overclock.net/forum/1805...l#post28424814 described at the 2nd half of the post
Hi Veii, can you please explain why you are recommending to have 50mV difference between CCD and IOD? As by any version of ryzen calculator is setting them equally just like by default on my MSI ACE board? Thanks
05-31-2020 05:03 PM
Veii
Quote: Originally Posted by TK421 View Post
Ok
The kit I have is 3600C16 2x16gb
So is running 1.45v daily safe? Assuming temp is below 42c
You can go between 1.42-1.46v without worrying about negative effects
You have to check how scaling behaves. Your kit might like 1.48v , or it might behave negative where only 1.46v is the sweetspot
1.42v wouldn't destabilize even at 50c, but memory is sensitive to temperature
At least 1.42v you can push, for more it depends on your cooling resolve and airflow + IC and PCB lottery luck

Higher than 1.48v depends afterwards on your PCB, tho B-dies have no stability issues with running 1.5v
Scaling is vague, depends on many things ~ try to find out yourself when they will destabilize
Dual rank likes less voltage and higher ClkDrvStrengh under CAD_BUS

@RaXelliX please check the PCB infront of you,
TB is accurate on the IC but it is not on the PCB revision
At best you could drop to 1.48v as 18nm isn't that big, but up to PCB ~ up to 1.52v shouldn't make issues for you, depends if A0 or X1/X2
05-31-2020 03:16 PM
TK421
Quote: Originally Posted by Veii View Post
Fully not
HynixMFR is the worst IC out there, alone by the age
But as its on the biggest nodesize - they seem to scale wonderfully above 1.6v
B-dies remain still the best choice when it comes to timing efficiency
= Maximum hit speed at X rated frequency

Memory runs in tiny 8+ decimal digit nanosecond values
It's true that some ICs perform better than others as the same frequency, same as dual rank technically is faster @ the same MT/s
But the biggest advantage of b-dies is their fast refresh cycle (tREFI) and low accepting tRFC (refresh pulses, explained stupidly)
Also their advantage is low PCB stress = less impedance required to drive them
Ultimately their scaling depends also on the PCB they are on
I think i just got extremely lucky to hit A1 pcb on the worst existing 266C16-18 HynixMFR kit out there ^^'
Yet it loved voltage

But you can't compare kits which require tRCD above 18-22 to function normally
Compared to B-dies which move in the range of 14-16
Technically speaking, Micron Rev.E kits are superior when it comes to pcb stress and so higher max frequency
But they hate voltage above 1.46v and so their tRCD and tRP are often very high, resulting in high delay timings
Even tho they appear faster , reality shows b-dies still win

Samsung released C-Dies near 2018~
as replacement for the already EOL B-dies which should be gone near Q1 2019
Around the time where Dram prices for good b-die kits peaked near 210$
A-die looks to be our new one, but yet B-die where scaling the best likely because of the node size
New A-die 17?nm doesn't like voltage that much, although the size flaw seems to have been fixed
~ soo it's not fully clear if they are better or not, the same goes for C-Die

If you want to check binning for a B-die kit for example, calculate frequency/tRCD=virtual value
Still you remain on the PCB luck, but at least you can try to measure a "dud" kit

Ok


The kit I have is 3600C16 2x16gb


So is running 1.45v daily safe? Assuming temp is below 42c
05-31-2020 03:11 PM
RaXelliX Much appreciated Veii. I will add Thaiphoon Burner screenshot later but it's a 18nm and im running it at 1.5v at the moment. 3200Mhz CL16 XMP @ 3733 CL16 tightened 16-20-20-36 and 1:1 with IF clock (1867Mhz).I have not tested voltage scaling tho.
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