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  Topic Review (Newest First)
05-26-2020 03:43 AM
Imprezzion
Quote: Originally Posted by munternet View Post
See if you can find the sweet spot for CL17
I managed to push it to 4200Mhz 17-17-17-34-320 with quite tight secondaries and tertiaries with Auto Optimized RTL/IO for now. It did a 500% 2h44m HCI run with no errors. I'll obviously do GSAT or something as well but this is a nice indication of general stability.

It did require me to bump from 1.46v to 1.50v on DRAM as 1.46v did error after like, 80% already. This is as high as CL17 will get me as even 4266 will go completely bonkers. I can't even pass a succesful Windows boot at 4266 with the same timings, even on 1.6v. So there's quite a wall there.

As my sig says i can get away with 16-17-17 on 4200 but it needs 1.54v at least and way way way looser secondaries. I can't get below 16 tWR or 18 tCWL for example on CL16 and it ends up being slower in AIDA.
05-26-2020 01:00 AM
robertr1
Quote: Originally Posted by Gen. View Post
I continue to test my memory (2 sticks from F4-3600C16Q-32GTZKK)
Have you done anything under dram timing control advanced settings? like slew rates, dram clock timers, termination voltages etc? Curious to know if you modified anything except for timings and voltages (dram/io/sa)
05-26-2020 12:53 AM
xSneak How are the new 10th gen cpus performing on memory overclocking? The core i7s and i9s have the upgraded memory controller supposedly.
05-26-2020 12:21 AM
fly1ngh1gh
Quote: Originally Posted by ogider View Post
fly1ngh1gh
I had comparable clock for 4x8 with z370 taichi and 8700k
For 2x16 I cant reach 4k. Sitting few months on this setting instead.

f4-3200c14d-32gtz
You need to pick up the resistance (RW, PARK, NOM), if you do not go higher in frequency. Correctly selected resistances give a boost in frequency. Unfortunately, I can't give you specific recommendations, because everything is individual on each system. You should also tweak the timings a little. You don't need to use 1T mode when selecting resistances, since this is an additional load for your memory.

Quote: Originally Posted by newls1 View Post
**EDIT** can twr be an even number like 16 too?
TWR is showing 17 in that pic, but in bios its set to 16. I set it to 15 in bios, and now its showing 16 in asrock timing config. I changed RTP to 8. So total changes are RTP = 8 and TWR = 16. im off to memtest.
You just have to follow these formulas for the Asus Board.
WTRS/L are installed in the BIOS via WRRDdg/sg according to the formula:

WRRD_sg=6+CWL+WTR_L
WRRD_dg=6+CWL+WTR_S

WR-install via WRPRE
WRPRE=4+CWL+WR
RTP-install via RDPRE
RDPRE=RTP
05-25-2020 08:12 PM
munternet
Quote: Originally Posted by ViTosS View Post
Just installed my Apex XI and it's running smooth, now to RAM OC, booted sucessfully at [email protected] (that wasn't possible boot over 4000Mhz no matter settings with my old Z370 Hero X), so where do I download just that TurboV Core app very clean and simple UI? I downloaded Asus Ai Suite 3 something like that and it has a bunch of other programs I don't need.
Try this
TurboV_Core_1.02.02.zip
05-25-2020 07:30 PM
ViTosS Just installed my Apex XI and it's running smooth, now to RAM OC, booted sucessfully at [email protected] (that wasn't possible boot over 4000Mhz no matter settings with my old Z370 Hero X), so where do I download just that TurboV Core app very clean and simple UI? I downloaded Asus Ai Suite 3 something like that and it has a bunch of other programs I don't need.
05-25-2020 06:25 PM
Jpmboy I know you guys in this thread are mainly doing 1151 and 1200 socketed gear (I do to )... but here's a compute box set up with 3 titan Vs, 7980XE and 64GB of ram. The IMC on this CPU is not as strong as on my 10980XE or 99--X for that matter, but damn this thing just crushes FP64 work.
I'm keeping the 3600c15 w/ tight secondaries for 24/7 and will further tune the 2h GSAT stable 3733c15, but the RTLs - well this board's A channel has a fast RTL vs the other 3. This was the same using 8GB sticks at the IMCs margin boundary. [email protected] or [email protected] channel A runs tight (always -2 vs the other 3). The IMC sets RTL and this is the clear margin edge for this board/cpu combo. Compute work requires a really stable system, and some of the stuff in Boinc for example will use up 30GB of ram (and heat sticks) pretty quiick. :O
Anyway - for your perusal.
16GB G.Skill Royals (RGB) - samsung B-die.
05-25-2020 05:31 PM
munternet
Quote: Originally Posted by Imprezzion View Post
I got pretty close to stability on 4500 18-18-18-36-400-2T but unfortunately it errors at ~250-300% passes in HCI. I'm already at 1.58v DRAM and 1.32v SA 1.27v IO. I really don't feel like going any higher lol. Not because of degradation or whatever, that's just part of overclocking a bit more "extremely" but because the DIMM's get close to the thermal instability point. Heck, the error might even be temp related as they did get up to about 47c during the test, even with my fan for the RAM running.

I did get 4500 19-19-19-39-400-2T at like, 1.55v to pass 1100% no errors but that isn't really "faster" latency wise compared to 4133 16-17-17 so..not sure if that is a good idea to run lol.

Time to continue tweaking random combinations of timings and frequencies tomorrow while working from home out of pure boredom.
See if you can find the sweet spot for CL17
05-25-2020 05:23 PM
BlueEarth It seems I have different opinion about tRAS compared to everyone else. It should be set as low as possible in the bios which is still stable.

First when you reduce tRAS lower, it will drive your L2 bandwidth higher without loss in anything else. In mainstream it is capped at 28 however in HEDT it is possible to set it below 28. The worst it can do is error like all other timings when set to low.

It is true that some formula can be used to determine good starting value however it is not absolute and that’s it, it is only starting value.

Why I came into such conclusion?

1. If you look into data sheet, tRAS is written as time (ns) and not number of clock (ns) which means it can be any arbitrary value no minimum clock. For comparison tFAW is written in both time (ns) and nck and if you go below the minimum nck (which is 16 in this case) you will lose performance of your L3 write.

2. If the chipset will cycle over when tRAS is too low it should behave like tFAW or tRRD where it doesn’t care even if you set it to 1. But with tRAS instead it will error out if too low showing that the chipset is not actually cycling trying to catch up.

3. Another look at the data sheet for example Samsung b-die (attached) reveal that higher stock frequency will have tCL, tRCD, tRP going up as well as expected however it has the tRAS lower. If tRAS somehow is derived from those it should also going up or at least the same if the increase is not significant, isn’t it?

4. Besides if there is exact super secret formula I think bios will simply not include it into the setting you can tweak (like tRC is not in Asus bios since it has definitive fixed formula of tRAS + tRP) or the value will be set automatically when you lower other related timings ala tWTR_S and L via tWRRD or tWR via tWRPRE and tCWL.

Probably I will get flame for this but before there is definitive proof and we still have tons of formula for it I stand by my experience.
05-25-2020 04:35 PM
Imprezzion I got pretty close to stability on 4500 18-18-18-36-400-2T but unfortunately it errors at ~250-300% passes in HCI. I'm already at 1.58v DRAM and 1.32v SA 1.27v IO. I really don't feel like going any higher lol. Not because of degradation or whatever, that's just part of overclocking a bit more "extremely" but because the DIMM's get close to the thermal instability point. Heck, the error might even be temp related as they did get up to about 47c during the test, even with my fan for the RAM running.

I did get 4500 19-19-19-39-400-2T at like, 1.55v to pass 1100% no errors but that isn't really "faster" latency wise compared to 4133 16-17-17 so..not sure if that is a good idea to run lol.

Time to continue tweaking random combinations of timings and frequencies tomorrow while working from home out of pure boredom.
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