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-   -   Preliminary view of AMD VEGA Bios (https://www.overclock.net/forum/67-amd/1633446-preliminary-view-amd-vega-bios.html)

gupsterg 06-30-2017 04:36 PM

Preliminary view of AMD VEGA Bios
 
8 Attachment(s)
OP reconstructed, some attachments/links still need resolving.

Last update: 29/10/18

Warning: Using this guide to edit your bios will void your warranty (if card has one). This guide is provided assuming a user knows implications of what they are doing. I accept no responsibility for damage from using this information. All efforts are being made to double check information but there maybe errors.

Make backup of original bios on video card, for each switch position.

Edit copies of your original bios, so you always have original unedited bios to use if things go bad.

Do not flash both bios positions, if something goes wrong you can use other switch position to boot and then change switch position and flash over bad ROM.



GPU-Z latest versions supports full VEGA ROM saving.

Support for flashing VEGA is only in AtiWinFlash v2.77 onwards. For flashing in W10 1803, AtiWinFlash v2.84 is needed (see TPU downloads section).


VEGA FE has a security feature to check VBIOS at post using a on die HW implementation, so modded VBIOS regardless of flash method is not working at present. RX VEGA also has this protection.

Attachment 188009

Flashing of unmodified VBIOS is functioning:-

i) RX VEGA editions can be flashed to another RX VEGA edition.
ii) VEGA FE editions can be flashed to another VEGA FE edition.

iii) Cross flashing between RX VEGA and VEGA FE is not possible.(Recently a 8GB FE VBIOS has surfaced this allows RX VEGA to be FE, link)

UEFI/GOP module can be updated, see Lordkag's tool in relevant section, also a shout to all that kept the tool going in his absence ;) and special thanks to facilitator Fernado of Win-Raid Forum!

Essentials

(Note: Some links still to be fixed)

https://github.com/torvalds/linux/bl...ga10_pptable.h

AtomBiosReader by Kizwan as in OP of Hawaii/Fiji bios editing OP

VEGA FE AIR shared by jstefanop

VEGA FE AIR with The Stilt's i2c comms unlock

VEGA FE LIQUID VBIOS on TPU

RX VEGA 56 AIR shared by Buildzoid

RX VEGA 64 AIR full ROM shared by Sicness

RX VEGA 64 AIR with The Stilt's i2c comms unlock

RX VEGA 64 AIO full ROM by kundica

RX VEGA 64 AIO V016.001.001.000.008774 by asder00

RX VEGA 64 Strix full ROM by hellm

VEGA_Soft_PP.zip 4k .zip file .

Hellm has created SoftPowerPlayTable key files. This PowerPlay in registry the driver will give priority over firmware PowerPlay. This is the same as on past cards where we used 'Extend Official Overclocking Limits' in MSI AB. It is a known workaround which does not cause issues to OS/driver. The registry PowerPlay can be modified like we would the VBIOS one, I will add guide soon, for now reference Linux VEGA PP linked above, info below and Hellm's post here and here.

Creating your own PowerPlay reg file



Useful links

RTG - Vega Whitepaper

https://en.wikipedia.org/wiki/Endianness

https://docs.mql4.com/basis/types/integer/integertypes

https://en.wikipedia.org/wiki/Byte

[Official] Vega Frontier / RX Vega Owners Thread

PCPer - Radeon Vega Frontier Edition GPU and PCB Exposed

Halsafar has created Vega64SoftPowerTableEditor, link to repository, link to compiled release and post within this thread. (Note: GTK# for .NET needed for app to work.)

Warning to VEGA FE owners GFX clocks section in Vega64SoftPowerTableEditor is not correct, only do PP mod reg edit by hand.

Viewing of VBIOS so far.

Spoiler!


Testing of PowerPlay registry mods

Spoiler!


Updating UEFI/GOP module in VBIOS

Spoiler!



Will be looking add other sections and VBIOS info soon as and when required :) . So do check OP for updates, usually I will bump thread with a post :) .

jstefanop 07-01-2017 12:41 AM

Cool I just got the card and glanced over the BIOS as well...ill start hacking the crap out of it and see what can be done. Memory can be pushed to about 1075mhz on stock BIOS, so going to see if its possible to control HBM2 voltage.

BTW voltage controller is IR 35217

gupsterg 07-01-2017 01:14 AM

Sweet smile.gif . Yeah that was last night before bedtime viewing wink.gif . Doing some more now wink.gif . You got some I2C dumps, etc to share smile.gif .

jstefanop 07-02-2017 07:44 PM

Quote:
Originally Posted by gupsterg View Post

Last update: 01/07/17


VddmemLookupTable has 1350mV, no idea if this is HBM voltage or something else. Fiji did not have HBM voltage in PowerPlay, nor was it 1.2V, but 1.3V. Not read about HBM2 at all TBH, but would have expected it lower or 1.3V, perhaps AMD needed to give it a bump if this values is indeed that.

.

Yes memory at 945mhz is indeed running at 1.36v according to my multimeter. This will be great if we can control memory voltage in bios finally. Dont know how much safe headroom there is for HBM2. Looks like its already pushed pretty high.

gupsterg 07-02-2017 11:41 PM

Fiji it was changeable via the voltage control chip using an offset register for loop 2. Fiji never had it in the PowerPlay it was changed via editing VoltagObjectInfo.

You have dual bios on card from when I viewed PCB images of PCPer.

i) When you dump bios using AtiWinFlash what size is it?
ii) Does AtiWinFlash v2.74 allow flashing of a dumped bios?

You could lower HBM2 voltage in PowerPlay and see if it has an effect wink.gif .

jstefanop 07-03-2017 03:26 PM

Yes there are two bios chips on the board toggle by switch, thankfully one of the chips are accessibly at the back of the PCB. No Atiflash support for vega. Flash image is 256kb pulled directly from chip. GPUZ downloads it as a 60kb image(probably a bug).

BTW haven't dissected the BIOS yet, but doing a quick glance I couldn't find the memory states. (neither the 167mhz base or 945 high state...Below are all the mem states driver returns:

0: 167Mhz *
1: 500Mhz
2: 800Mhz
3: 945Mhz

gupsterg 07-03-2017 04:05 PM

PowerPlay header was in OP ~3 days ago.

Code:
6A 01 (0x16Ah)          USHORT usMclkDependencyTableOffset;        /* points to ATOM_Vega10_MCLK_Dependency_Table */


Once you copy out PowerPlay within it at offset location 16A is Mclk table.




Code:
01 04 3C 41 00 00 00 00 00 50 C3 00 00 01 00 00 80 38 01 00 02 00 00 24 71 01 00 03 00 00

MCLK_Dependency_Table (Click to show)
Code:
typedef struct _ATOM_Vega10_MCLK_Dependency_Table {
01    UCHAR ucRevId;
04    UCHAR ucNumEntries;                                         /* Number of entries. */
    ATOM_Vega10_MCLK_Dependency_Record entries[1];            /* Dynamically allocate entries. */
} ATOM_Vega10_MCLK_Dependency_Table;

typedef struct _ATOM_Vega10_MCLK_Dependency_Record {
3C 41 00 00 (167MHz)    ULONG  ulMemClk;                                            /* Clock Frequency */
00                      UCHAR  ucVddInd;                                            /* SOC_VDD index */
00                      UCHAR  ucVddMemInd;                                         /* MEM_VDD - only non zero for MCLK record */
00                      UCHAR  ucVddciInd;                                          /* VDDCI   = only non zero for MCLK record */
} ATOM_Vega10_MCLK_Dependency_Record;

typedef struct _ATOM_Vega10_MCLK_Dependency_Record {
50 C3 00 00 (500MHz)    ULONG  ulMemClk;                                            /* Clock Frequency */
01                      UCHAR  ucVddInd;                                            /* SOC_VDD index */
00                      UCHAR  ucVddMemInd;                                         /* MEM_VDD - only non zero for MCLK record */
00                      UCHAR  ucVddciInd;                                          /* VDDCI   = only non zero for MCLK record */
} ATOM_Vega10_MCLK_Dependency_Record;

typedef struct _ATOM_Vega10_MCLK_Dependency_Record {
80 38 01 00 (800MHz)    ULONG  ulMemClk;                                            /* Clock Frequency */
02                      UCHAR  ucVddInd;                                            /* SOC_VDD index */
00                      UCHAR  ucVddMemInd;                                         /* MEM_VDD - only non zero for MCLK record */
00                      UCHAR  ucVddciInd;                                          /* VDDCI   = only non zero for MCLK record */
} ATOM_Vega10_MCLK_Dependency_Record;

typedef struct _ATOM_Vega10_MCLK_Dependency_Record {
24 71 01 00 (945MHz)    ULONG  ulMemClk;                                            /* Clock Frequency */
03                      UCHAR  ucVddInd;                                            /* SOC_VDD index */
00                      UCHAR  ucVddMemInd;                                         /* MEM_VDD - only non zero for MCLK record */
00                      UCHAR  ucVddciInd;                                          /* VDDCI   = only non zero for MCLK record */
} ATOM_Vega10_MCLK_Dependency_Record;


Nice it has several HBM states smile.gif , I did do a Fiji ROM that way as well for testing, video in Fiji thread wink.gif . I'll see if I can gain AtiWinFlash with support, otherwise case of waiting wink.gif .

jstefanop 07-03-2017 04:25 PM

Ahh im an idiot...was searching for 945 instead of 94500 biggrin.gif

So SM dumps via AIDA and msi show nothing on the IR35217, so either its not exposed or somehow locked.

Either way I can flash directly so no need for atiflash..ill start playing soon and see what can be controlled via BIOS.

gupsterg 07-03-2017 04:34 PM

NP smile.gif.

I reckon i2c unsupported at present by apps. Even latest AIDA64 does not get i2c on Fiji, only MSI AB has done since that GPU launched. Polaris IIRC is hit'n'miss which app get dumps IIRC, not paid too much attention to Polaris stuff TBH.

I sent the request anyway, if it bears fruit be nice wink.gif .

Sweet you have Blackcat or differing flash tool? I gotta get one wink.gif .

xkm1948 07-03-2017 05:08 PM

Wait so you got a VEGA FE after all? Congrats!thumb.gif


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